New mathematical formulation for designing a fully differential self-biased folded cascode amplifier

One of the most important building blocks in analog circuit design is the operational amplifiers. This is because of their versatility and wide spread usage in many applications such as communications transmitters and receivers, analog to digital converters, or any other application that requires a small signal to be amplified. The basic amplifier topologies are introduced. Then, some operational amplifiers topologies are introduced with some techniques to self bias these amplifiers. The folded cascode fully differential Op-Amp with self bias is presented. This is one of the newest amplifier topologies which provide stable self-biased amplifiers. A new mathematical model for fully differential folded cascode amplifiers is presented and generalized to include the family of fully differential complementary amplifiers. This formulation focuses on deriving detailed design equations for the amplifier gain and frequency response. The equations are verified through time domain and frequency domain simulations of different fabrication processes to ensure the validity of the model across a wide range of processes. The model was verified against TMSC 180nm, 250nm, and 350nm fabrication processes. The new model agrees well with simulations; with 1% error for the amplifier gain and \u3c7% error for amplifier bandwidth. The relatively high error value for the bandwidth is because the model considers the worst case scenario and overestimates the output capacitance. Finally, the algorithm of getting this formulation is extended to include special and commonly used cases. This formulation proved to be very useful in designing stable, self-biased, fully differential folded cascode amplifiers

CMOS Non-tailed differential pair

A continuous-time complementary metal-oxide-semiconductor differential pair that does not require the traditional tail current source as a way to control the direct current and common-mode current is presented. Compared with a p-channel long-tailed pair, the proposed non-tailed solution operates under a higher maximum input common-mode voltage that includes (V-DD+V-SS)/2 even under low supply voltages. Experimental measurements on a prototype fabricated in a 0.35-mu m technology (with metal-oxide-semiconductor thresholds greater than 0.6V) confirm this behavior for supply voltages as low as 1.2V, whereas the long-tailed pair with the same technology offers the same capability only for supplies higher than 1.6V

Generation of analog voltages to improve flash memory read speed

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science; and, Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.Includes bibliographical references (p. 120-121).by Michelle Ying-Wai Eng.B.S.M.Eng

First order sigma-delta modulator of an oversampling ADC design in CMOS using floating gate MOSFETS

We report a new architecture for a sigma-delta oversampling analog-to-digital converter (ADC) in which the first order modulator is realized using the floating gate MOSFETs at the input stage of an integrator and the comparator. The first order modulator is designed using an 8 MHz sampling clock frequency and implemented in a standard 1.5µm n-well CMOS process. The decimator is an off-chip sinc-filter and is programmed using the VERILOG and tested with Altera Flex EPF10K70RC240 FPGA board. The ADC gives an 8-bit resolution with a 65 kHz bandwidth

DESIGNING LOW VOLTAGE AND POWER CMOS OP AMP

The importance of using low supply voltage for analogue circuit has enormously increased in recent past. The recent trend shows that a supply voltage can be degraded until 1.5 V. Low power consumption also important to increase the battery life, the packaging density and circuit reliability. CMOS op amp technology today can have power consumption lower than 200 uW. The objective of this project is to design low supply voltage and low power consumption CMOS operational amplifier. Low supply voltage op amp with 1.6 V has been successfully designed. The design was using bulk-driven PMOS transistors as an input differential of the op amp. The compensation capacitor was also used to control the power consumption. The op amp is capable of producing low power consumption of 20 uAV. The layout was design using 0.35 urn technology and have gone through DRC and LVS check. Software Virtuoso Schematic Capture and Virtuoso Spectre Circuit Simulator from cadence have been used for schematic capture and design simulation. For layout design, DRC and LVS check, softwere Calibre from Mentor Graphic have been used. I

High Performance Optical Transmitter Ffr Next Generation Supercomputing and Data Communication

High speed optical interconnects consuming low power at affordable prices are always a major area of research focus. For the backbone network infrastructure, the need for more bandwidth driven by streaming video and other data intensive applications such as cloud computing has been steadily pushing the link speed to the 40Gb/s and 100Gb/s domain. However, high power consumption, low link density and high cost seriously prevent traditional optical transceiver from being the next generation of optical link technology. For short reach communications, such as interconnects in supercomputers, the issues related to the existing electrical links become a major bottleneck for the next generation of High Performance Computing (HPC). Both applications are seeking for an innovative solution of optical links to tackle those current issues. In order to target the next generation of supercomputers and data communication, we propose to develop a high performance optical transmitter by utilizing CISCO Systems®\u27s proprietary CMOS photonic technology. The research seeks to achieve the following outcomes: 1. Reduction of power consumption due to optical interconnects to less than 5pJ/bit without the need for Ring Resonators or DWDM and less than 300fJ/bit for short distance data bus applications. 2. Enable the increase in performance (computing speed) from Peta-Flop to Exa-Flops without the proportional increase in cost or power consumption that would be prohibitive to next generation system architectures by means of increasing the maximum data transmission rate over a single fiber. 3. Explore advanced modulation schemes such as PAM-16 (Pulse-Amplitude-Modulation with 16 levels) to increase the spectrum efficiency while keeping the same or less power figure. This research will focus on the improvement of both the electrical IC and optical IC for the optical transmitter. An accurate circuit model of the optical device is created to speed up the performance optimization and enable co-simulation of electrical driver. Circuit architectures are chosen to minimize the power consumption without sacrificing the speed and noise immunity. As a result, a silicon photonic based optical transmitter employing 1V supply, featuring 20Gb/s data rate is fabricated. The system consists of an electrical driver in 40nm CMOS and an optical MZI modulator with an RF length of less than 0.5mm in 0.13&mu m SOI CMOS. Two modulation schemes are successfully demonstrated: On-Off Keying (OOK) and Pulse-Amplitude-Modulation-N (PAM-N N=4, 16). Both versions demonstrate signal integrity, interface density, and scalability that fit into the next generation data communication and exa-scale computing. Modulation power at 20Gb/s data rate for OOK and PAM-16 of 4pJ/bit and 0.25pJ/bit are achieved for the first time of an MZI type optical modulator, respectively

Diseño e implementación de un rectificador trifásico totalmente controlado para el control de un motor DC

[ES] En este trabajo se realizará un modelado de un convertidor ca/cc trifásico de onda completa totalmente controlado por medio de tiristores para poner en funcionamiento un motor de corriente continua además de un control PI para la regulación de velocidad en bucle cerrado. La necesidad de implementar un regulador viene dada a la inestabilidad de funcionamiento del motor en bucle abierto.Novella Ruiz, J. (2016). Diseño e implementación de un rectificador trifásico totalmente controlado para el control de un motor DC. Universitat Politècnica de València. http://hdl.handle.net/10251/76092TFG

Novel approaches in current-feedback operational amplifier design

The aim of this research programme was to design and develop a novel bipolar junction transistor Current Feedback Operational Amplifier (CFOA) with a good Common-Mode Rejection Ratio (CMRR), suitable for radio frequency (RF) applications. This research focused on investigation of the established CFOA with the emphases of improving CMRR, bandwidth, Voltage-Offset and Slew-rate performance. The majority of the results of this work have been reported by the author in references [11 to [6]. Initially a thorough analysis of the conventional CFOA was undertaken to provide an in depth understanding of the amplifier's operation, and this work revealed that the main shortcomings of the CFOA are in the design of the input stage. This initial study focussed on establishing reasons for the poor DC offset-voltage performance and CMRR and confirmed that these designs have inherently poor performance in these two elements. The analysis was carried out using both theoretical modelling and computer simulation. Using this analysis of the conventional CFOA as a benchmark, various novel circuit techniques were investigated. Several new input circuits for the CFOA were proposed with respect to improving the three previously mentioned key characteristics, viz., CMRR, offset voltage, and slew-rate. The first technique explored is based on floating the entire input stage of the CFOA which yielded significant improvements in CMRR, Offset-Voltage and bandwidth, and the results of this workwere published in [11, [2], and P). Based on these initial findings a second major development was undertaken. This time a bootstrapping technique was employed to key sections of the input stage, leading to new, simplified input circuit topology. This development leads to low DC offset voltage, wide bandwidth and high CNIRR, as well as improved gain accuracy, and was published by the author in [4,5]. A logical approach to the different input stage architectures examined by the author resulted in identification of a hierarchy of 6 different input CFOA circuit designs and a comparative study was undertaken showing their relative performance in respect of CMRR, Offset-Voltage and Slew-rate. This work was presented by the author, [6]