Characterization of 28 nm FDSOI MOS and application to the design of a low-power 2.4 GHz LNA

IoT is expected to connect billions of devices all over world in the next years, and in a near future, it is expected to use LR-WPAN in a wide variety of applications. Not all the devices will require of high performance but will require of low power hungry systems since most of them will be powered with a battery. Conventional CMOS technologies cannot cover these needs even scaling it to very small regimes, which appear other problems. Hence, new technologies are emerging to cover the needs of this devices. One promising technology is the UTBB FDSOI, which achieves good performance with very good energy efficiency. This project characterizes this technology to obtain a set of parameters of interest for analog/RF design. Finally, with the help of a low-power design methodology (gm/Id approach), a design of an ULP ULV LNA is performed to check the suitability of this technology for IoT

Design of a RF communication receiver front-end for ultra-low power and voltage applications in a FDSOI 28nm technology

The advances in the semiconductor and wireless industry have enabled the expansion of new paradigms, which have given rise to concepts like Internet of Things (IoT). Apart from qualities like size, speed or cost, the ever-increasing demand for autonomy focuses all design efforts in the minimization of power consumption. Scaling technologies and the request to reduce power consumption have pushed designers towards lower supply voltages. Despite the fact that technology scalability allows for faster transistors, radio-frequency (RF) integrated circuit (IC) design accuses the reduction of the voltage supply through frequency response degradation, which significantly deteriorates the overall performance. Analog and RF circuits in highend applications require substantial gate voltage overdrive to maintain device speed, which further complicates the design due to the reduction of voltage headroom. As a consequence, the necessity to develop circuit topologies capable to deal with low-power and low-voltage stringent constraints well suited to applications requiring long battery life and low cost emerges. This work aims to implement a low-noise amplifier and mixer stages of a radio-frequency receiver front-end working under an ultra-low power (< 100 ?W) and ultra-low voltage (< 0.8V) scenario while targeting decent overall performance. To cope with the stringent power requirements, 28nm FD-SOI technology will be used to take maximum profit of aggressive forward body bias and enhance transistor performance

Metodologia Per la Caratterizzazione di amplificatori a basso rumore per UMTS

In questo lavoro si presenta una metodologia di progettazione elettronica a livello di sistema, affrontando il problema della caratterizzazione dello spazio di progetto dell' amplificatore a basso rumore costituente il primo stadio di un front end a conversione diretta per UMTS realizzato in tecnologia CMOS con lunghezza di canale .18u. La metodologia è sviluppata al fine di valutare in modo quantititativo le specifiche ottime di sistema per il front-end stesso e si basa sul concetto di Piattaforma Analogica, che prevede la costruzione di un modello di prestazioni per il blocco analogico basato su campionamento statistico di indici di prestazioni del blocco stesso, misurati tramite simulazione di dimensionamenti dei componenti attivi e passivi soddisfacenti un set di equazioni specifico della topologia circuitale. Gli indici di prestazioni vengono successivamente ulizzati per parametrizzare modelli comportamentali utilizzati nelle fasi di ottimizzazione a livello di sistema. Modelli comportamentali atti a rappresentare i sistemi RF sono stati pertanto studiati per ottimizzare la scelta delle metriche di prestazioni. L'ottimizzazione dei set di equazioni atti a selezionare le configurazione di interesse per il campionamento ha al tempo stesso richiesto l'approfondimento dei modelli di dispositivi attivi validi in tutte le regioni di funzionamento, e lo studio dettagliato della progettazione degli amplificatori a basso rumore basati su degenerazione induttiva. Inoltre, il problema della modellizzazione a livello di sistema degli effetti della comunicazione tra LNA e Mixer è stato affrontato proponendo e analizzando diverse soluzioni. Il lavoro ha permesso di condurre un'ottimizzazione del front-end UMTS, giungendo a specifiche ottime a livello di sistema per l'amplificatore stesso

Ultra Small Antenna and Low Power Receiver for Smart Dust Wireless Sensor Networks

Wireless Sensor Networks have the potential for profound impact on our daily lives. Smart Dust Wireless Sensor Networks (SDWSNs) are emerging members of the Wireless Sensor Network family with strict requirements on communication node sizes (1 cubic centimeter) and power consumption (< 2mW during short on-states). In addition, the large number of communication nodes needed in SDWSN require highly integrated solutions. This dissertation develops new design techniques for low-volume antennas and low-power receivers for SDWSN applications. In addition, it devises an antenna and low noise amplifier co-design methodology to increase the level of design integration, reduce receiver noise, and reduce the development cycle. This dissertation first establishes stringent principles for designing SDWSN electrically small antennas (ESAs). Based on these principles, a new ESA, the F-Inverted Compact Antenna (FICA), is designed at 916MHz. This FICA has a significant advantage in that it uses a small-size ground plane. The volume of this FICA (including the ground plane) is only 7% of other state-of-the-art ESAs, while its efficiency (48.53%) and gain (-1.38dBi) are comparable to antennas of much larger dimensions. A physics-based circuit model is developed for this FICA to assist system level design at the earliest stage, including optimization of the antenna performance. An antenna and low noise amplifier (LNA) co-design method is proposed and proven to be valid to design low power LNAs with the very low noise figure of only 1.5dB. To reduce receiver power consumption, this dissertation proposes a novel LNA active device and an input/ouput passive matching network optimization method. With this method, a power efficient high voltage gain cascode LNA was designed in a 0.13um CMOS process with only low quality factor inductors. This LNA has a 3.6dB noise figure, voltage gain of 24dB, input third intercept point (IIP3) of 3dBm, and power consumption of 1.5mW at 1.0V supply voltage. Its figure of merit, using the typical definition, is twice that of the best in the literature. A full low power receiver is developed with a sensitivity of -58dBm, chip area of 1.1mm2, and power consumption of 2.85mW

Improving the accuracy of RF alternate test using multi-VDD conditions: application to envelope-based test of LNAs

Trabajo presentado al "20 Asina Test Symposium" celebrado en Nueva Delhi (India) del 20 al 23 de Noviembre del 2011.-- Reprinted from (relevant publication info). This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the products or services of CSIC Spanish National Research Council, Digital.CSIC. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected]. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.This work demonstrates that multi-VDD conditions may be used to improve the accuracy of machine learning mod- els, significantly decreasing the prediction error. The proposed technique has been successfully applied to a previous alternate test strategy for LNAs based on response envelope detection. A prototype has been developed to show its feasibility. The prototype consists of a low-power 2.4GHz LNA and a simple envelope detector, integrated in a 90nm CMOS technology. Post- layout simulation results are provided to verify the functionality of the approach. Copyright © 2011 IEEE.This work has been partially funded by a CSIC JAE-Doc contract (cofinanced by FSE), a Spanish MAE-AECID grant and projects: SR2 - Short Range Radio (Catrene European project 2A105SR2 and Avanza I+D Spanish project TSI-020400-2010-55, cofinanced with FEDER program), Auto-calibración y auto-test en circuitos analógicos, mixtos y de radio frecuencia (Andalusian Government project P09-TIC-5386, cofinanced with FEDER program), and Catrene project TOETS (CT 302).Peer reviewe

Wideband CMOS low noise amplifiers

Modern fully integrated receiver architectures, require inductorless circuits to achieve their potential low area, low cost, and low power. The low noise amplifier (LNA), which is a key block in such receivers, is investigated in this thesis. LNAs can be either narrowband or wideband. Narrowband LNAs use inductors and have very low noise figure, but they occupy a large area and require a technology with RF options to obtain inductors with high Q. Recently, wideband LNAs with noise and distortion cancelling, with passive loads have been proposed, which can have low NF, but have high power consumption. In this thesis the main goal is to obtain a very low area, low power, and low-cost wideband LNA. First, it is investigated a balun LNA with noise and distortion cancelling with active loads to boost the gain and reduce the noise figure (NF). The circuit is based on a conventional balun LNA with noise and distortion cancellation, using the combination of a common-gate (CG) stage and common-source (CS) stage. Simulation and measurements results, with a 130 nm CMOS technology, show that the gain is enhanced by about 3 dB and the NF is reduced by at least 0.5 dB, with a negligible impact on the circuit linearity (IIP3 is about 0 dBm). The total power dissipation is only 4.8 mW, and the active area is less than 50 x 50 m2 . It is also investigated a balun LNA in which the gain is boosted by using a double feedback structure.We propose to replace the load resistors by active loads, which can be used to implement local feedback loops (in the CG and CS stages). This will boost the gain and reduce the noise figure (NF). Simulation results, with the same 130 nm CMOS technology as above, show that the gain is 24 dB and NF is less than 2.7 dB. The total power dissipation is only 5.4 mW (since no extra blocks are required), leading to a figure-of-merit (FoM) of 3.8 mW1, using 1.2 V supply. The two LNA approaches proposed in this thesis are validated by simulation and by measurement results, and are included in a receiver front-end for biomedical applications (ISM and WMTS), as an example; however, they have a wider range of applications

Low Power Adaptive Circuits: An Adaptive Log Domain Filter and A Low Power Temperature Insensitive Oscillator Applied in Smart Dust Radio

This dissertation focuses on exploring two low power adaptive circuits. One is an adaptive filter at audio frequency for system identification. The other is a temperature insensitive oscillator for low power radio frequency communication. The adaptive filter is presented with integrated learning rules for model reference estimation. The system is a first order low pass filter with two parameters: gain and cut-off frequency. It is implemented using multiple input floating gate transistors to realize online learning of system parameters. Adaptive dynamical system theory is used to derive robust control laws in a system identification task. Simulation results show that convergence is slower using simplified control laws but still occurs within milliseconds. Experimental results confirm that the estimated gain and cut-off frequency track the corresponding parameters of the reference filter. During operation, deterministic errors are introduced by mismatch within the analog circuit implementation. An analysis is presented which attributes the errors to current mirror mismatch. The harmonic distortion of the filter operating in different inversion is analyzed using EKV model numerically. The temperature insensitive oscillator is designed for a low power wireless network. The system is based on a current starved ring oscillator implemented using CMOS transistors instead of LC tank for less chip area and power consumption. The frequency variance with temperature is compensated by the temperature adaptive circuits. Experimental results show that the frequency stability from 5°C to 65°C has been improved 10 times with automatic compensation and at least 1 order less power is consumed than published competitors. This oscillator is applied in a 2.2GHz OOK transmitter and a 2.2GHz phase locked loop based FM receiver. With the increasing needs of compact antenna, possible high data rate and wide unused frequency range of short distance communication, a higher frequency phase locked loop used for BFSK receiver is explored using an LC oscillator for its capability at 20GHz. The success of frequency demodulation is demonstrated in the simulation results that the PLL can lock in 0.5&mu;s with 35MHz lock-in range and 2MHz detection resolution. The model of a phase locked loop used for BFSK receiver is analyzed using Matlab

Study Of Nanoscale Cmos Device And Circuit Reliability

The development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability issues caused by voltage and/or temperature stress are gate oxide breakdown (BD), hot carrier effects (HCs), and negative bias temperature instability (NBTI). They become even more important for the nanoscale CMOS devices, because of the high electrical field due to the small device size and high temperature due to the high transistor densities and high-speed performances. This dissertation focuses on the study of voltage and temperature stress-induced reliability issues in nanoscale CMOS devices and circuits. The physical mechanisms for BD, HCs, and NBTI have been presented. A practical and accurate equivalent circuit model for nanoscale devices was employed to simulate the RF performance degradation in circuit level. The parameter measurement and model extraction have been addressed. Furthermore, a methodology was developed to predict the HC, TDDB, and NBTI effects on the RF circuits with the nanoscale CMOS. It provides guidance for the reliability considerations of the RF circuit design. The BD, HC, and NBTI effects on digital gates and RF building blocks with the nanoscale devices low noise amplifier, oscillator, mixer, and power amplifier, have been investigated systematically. The contributions of this dissertation include: It provides a thorough study of the reliability issues caused by voltage and/or temperature stresses on nanoscale devices from device level to circuit level; The more real voltage stress case high frequency (900 MHz) dynamic stress, has been first explored and compared with the traditional DC stress; A simple and practical analytical method to predict RF performance degradation due to voltage stress in the nanoscale devices and RF circuits was given based on the normalized parameter degradations in device models. It provides a quick way for the designers to evaluate the performance degradations; Measurement and model extraction technologies, special for the nanoscale MOSFETs with ultra-thin, ultra-leaky gate oxide, were addressed and employed for the model establishments; Using the present existing computer-aided design tools (Cadence, Agilent ADS) with the developed models for performance degradation evaluation due to voltage or/and temperature stress by simulations provides a potential way that industry could use to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of nanotechnology, and scientists and engineers have been exploring here for years. The reliability is the first challenge for the commercialization of the nanoscale CMOS devices, which will be further downscaling into several tens or ten nanometers. The reliability is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation, from device level to circuit level, provide not only an insight on how the voltage and/or temperature stress effects on the performances, but also methods and guidance for the designers to achieve more reliable circuits with nanoscale MOSFETs in the future

Methods and tools for the design of RFICs

Ambient intelligence is going to focus the next advances in wireless technologies. Hence, the increasing demand on radio frequency (RF) devices and applications represents, not only a challenge for technological industries to improve its roadmaps, but also for RF engineers to design more robust, low-power, small-size and low-cost devices. Regarding to communication robustness, in the latest years, differential topologies have acquired an important relevance because of its natural noise and interference immunity. Within this framework, a differential n-port device can still be treated with the classical analysis circuit theory by means of Z-,Y-, h-parameters or the most suitable S-parameters in the radio frequency field. Despite of it, Bockelman introduced the mixed-mode scattering parameters, which more properly express the differential and common-mode behavior of symmetrical devices. Since then, such parameters have been used with a varying degree of success, as it will be shown, mainly because of a misinterpretation. Thereby, this thesis is devoted to extend the theory of mixed-mode scattering parameters and proposes the methodology to analyze such devices. For this proposal, the simplest case of a two-port device is developed. By solving this simple case, most of the lacks of the current theory are filled up. As instance, it allows the characterization and comparison of symmetric and spiral inductors, which have remained a controversy point until now. After solving this case, the theory is extended to a n-port device. Another key point on the fast and inexpensive development of radio frequency devices is the advance on fast CAD tools for the analysis and synthesis of passive devices. In the case of silicon technologies, planar inductors have become the most popular shapes because of its integrability. However, the design of inductors entails a deep experience and acknowledge not only on the behavior of such devices but on the use of electromagnetic (EM) simulators. Unfortunately, the use of EM simulators consumes an important quantity of time and resources. Thereby, this thesis is devoted to improve some of the aspects that slow down the synthesis process of inductors. Therefore, an ‘ab initio’ technique for the meshing of planar radio frequency and microwave circuits is described. The technique presented can evaluate the losses in the component with a high accuracy just in few seconds where an electromagnetic simulator would normally last hours. Likewise, a simple bisection algorithm for the synthesis of compact planar inductors is presented. It is based on a set of heuristic rules obtained from the study of the electromagnetic behavior of these planar devices. Additionally, design of a single-ended to differential low noise amplifier (LNA) in a CMOS technology is performed by using the methods and tools described.L'enginyeria de radiofreqüència i la tecnologia de microones han assolit un desenvolupament inimaginable i avui en dia formen part de la majoria de les nostres activitats diàries. Probablement, la tecnologia mòbil ha tingut un desenvolupament més ràpid que qualsevol altre avenç tecnològic de l'era digital. Avui en dia, podem dir que el paradigma de la mobilitat s'ha assolit i tenim accés ràpid a internet des de qualsevol lloc on podem estar amb un dispositiu de butxaca. No obstant això, encara hi ha fites per endavant. Es més que probable que el paradigma de l’ "ambient intelligence” sigui el centre dels pròxims avenços en les tecnologies sense fils. A diferencia del paradigma de l"ambient intelligence', l'evolució de la tecnologia de la informació mai ha tingut l'objectiu explícit de canviar la societat, sinó que ho van fer com un efecte secundari, en canvi, les visions d' “ambient intelligence” proposen expressament el transformar la societat mitjançant la connexió completa i la seva informatització. Per tant, l'augment de la demanda de dispositius de ràdio freqüència (RF) i de les seves possibles aplicacions representa, no només un repte per a les indústries tecnològiques per millorar els seus plans de treball, sinó també per als enginyers de RF que hauran de dissenyar dispositius de baixa potència, més robusts, de mida petita i de baix cost. Quant a la robustesa dels dispositius, en els últims anys, les topologies de tipus diferencial han adquirit una important rellevància per la seva immunitat natural al soroll i resistència a les interferències. Dins d'aquest marc, un dispositiu de nports diferencial, encara pot ser tractat com un dispositiu 2nx2n i la teoria clàssica d'anàlisi de circuits (és a dir, la temia de quadripols) es pot aplicar a través de paràmetres Z, Y, h o els paràmetres S, més adequats en el camp de freqüència de ràdio. Tot i això, Bockelman i Eisenstadt introdueixen els paràmetres S mixtos, que expressen més adequadament el comportament diferencial i en mode comú de dispositius simètrics o asimètrics. Des de llavors, aquests paràmetres s'han utilitzat amb un grau variable d'èxit, com es mostrarà, principalment a causa d'una mala interpretació. D'aquesta manera, la primera part d'aquesta tesi està dedicada a estendre la teoria dels paràmetres S de mode mixt i proposa la metodologia d'anàlisi d'aquest tipus de dispositius i circuits. D'aquesta forma, en el Capítol 2, es desenvolupa el cas més simple d'un dispositiu de dos ports. En resoldre aquest cas simple, la major part de les mancances de la teoria actual es posen de relleu. Com a exemple, pennet la caracterització i la comparació de bobines simètriques i espiral no simètriques, que han estat un punt de controvèrsia fins ara. Després de resoldre aquest cas, al Capítol 3 s'estén la teOIia a un dispositiu de n-ports dels quals un nombre pot ser single-ended i la resta diferencials. És en aquest moment quan la dualitat existent entre els paràmetres S estàndard i de mode mixt es pot veure clarament i es destaca en el seu conjunt. Aquesta teoria permet, tanmateix, estendre la teoria clàssica d'amplificadors quan s'analitzen per mitjà de paràmetres S. Un altre punt clau en el desenvolupament ràpid i de baix cost dels dispositius de radiofreqüència és l'avenç en les eines CAD ràpides per a l'anàlisi i síntesi dels dispositius passius, en especial dels inductors. Aquests dispositius apareixen tot sovint en el disseny de radio freqüència degut a la seva gran versatilitat. Tot i que hi ha hagut múltiples intents de reemplaçar amb components externs o circuits, fins i tot actius, en el cas de les tecnologies de silici, els inductors planars s'han convertit en les formes més populars per la seva integrabilitat. No obstant això, el disseny d'inductors implica conèixer i posseir una experiència profunda no només en el comportament d'aquests dispositius, però també en l'ús de simuladors electromagnètics (EM). Desafortunadament, l'ús dels simuladors EM consumeix una quantitat important de temps i recursos. Per tant, la síntesi dels inductors representa un important inconvenient actualment. D'aquesta manera, la segona part d'aquesta tesi està dedicada a millorar alguns dels aspectes que frenen el procés de síntesi dels inductors. Per tant, en el Capítol 4, es descriu una tècnica 'ab initio' de generació de la malla per bobines planars en ràdio freqüència i microones. La tècnica es basa en l'estudi analític dels fenòmens d'aglomeració de corrent que tenen lloc a l'interior del component. En aquesta avaluació, no es requereix una solució explícita dels corrents i de les càrregues arreu del circuit. Llavors, el nombre de cel•les de la malla assignades a una tira de metall donada, depèn del valor inicialment obtingut a partir de l'estudi analític. La tècnica presentada pot avaluar les pèrdues en el component amb una gran precisió només en uns pocs segons, quan comparat amb un simulador electromagnètic normalment es necessitaria hores. De la mateixa manera, en el Capítol 5 es presenta un senzill algoritme de bisecció per a la síntesi d'inductors planars compactes. Es basa en un conjunt de regles heurístiques obtingut a partir de l'estudi del comportament electromagnètic d'aquests dispositius planars. D'aquesta manera, el nombre d'iteracions es manté moderadament baix.D'altra banda, per tal d'accelerar l'anàlisi en cada pas, s'utilitza un simulador ràpid electromagnètic planar, el qual es basa en el coneixement que es té del component sintetitzat. Finalment, en el Capítol 6, la metodologia de paràmetres S de mode mixt proposada i les eines CAD introduides s'utilitzen àmpliament en el disseny d'un amplificador de baix soroll “single-ended” a diferencial (LNA), mitjançant una tecnologia estàndard CMOS.L'amplificador de baix soroll és un dels components claus en un sistema de recepció de radio freqüència, ja que tendeix a dominar la sensibilitat i la figura de soroll (NF) de tot el sistema. D'altra banda, les característiques d'aquest circuit estan directament relacionades amb els components actius i passius disponibles en una tecnologia donada. Per tant, la tecnologia escollida, el factor de qualitat dels passius, i la forma com es caracteritzen tindran un alt impacte en les principals figures de mèrit del circuit real