Design guidelines for reconfigurable multiplier blocks

The newly proposed reconfigurable multiplier blocks offer significant savings in area over the traditional multiplier blocks for time-multiplexed digital filters or any other system where only a subset of the coefficients that can be produced by the multiplier block is needed in a given time. The basic structure comprises a multiplexer connected to at least one input of an adder/subtractor that can generate several partial products, leading to better area utilization. The multiplier block algorithm complexity of a design increases logarithmically as the number of the multiplexers is increased. Design guidelines for the maximum utilization of the reconfigurable multiplier block structures are also presented

Synthesis of reconfigurable multiplier blocks: part I: fundamentals

Reconfigurable Multiplier Blocks (ReMB) offer significant area, delay and possibly power reduction in time multiplexed implementation of multiple constant multiplications. This paper and its companion paper (subtitled Part II- Algorithm) together present a systematic synthesis method for Single Input Single Output (SISO) and Single Input Multiple Output (SIMO) ReMB designs. This paper presents the necessary foundation and terminology needed for developing a systematic synthesis technique. The companion paper illustrates the synthesis method through examples. The method proposed achieves reduced logic-depth and area over standard multipliers / multiplier blocks

Reconfigurable implementation of recursive DCT kernels for reduced quantization noise

Time multiplexed implementations of the recursive DCT processors are widely used in many multimedia and compression applications. Recently proposed three Goertzel kernels offer significant improvement (up to 90 %) in the noise performance of the time-multiplexed architecture to allow word-length specifications get reduced. In this paper, a highly optimized reconfigurable DCT architecture is proposed that can perform the function of three different kemels (Type A, B and C) on Virtex FPG

Reconfigurable Adaptive Multiple Transform Hardware Solutions for Versatile Video Coding

Computer aided design is nowadays a must to quickly provide optimized circuits, to cope with stringent time to market constraints, and to be able to guarantee colliding constrained requirements. Design automation is exploited, whenever possible, to speed up the design process and relieve the developers from error prone customization, optimization and tuning phases. In this work we study the possibility of adopting automated algorithms for the optimization of reconfigurable multiple constant multiplication circuits. In particular, an exploration of novel reconfigurable Adaptive Multiple Transform circuital solutions adoptable in video coding applications has been conducted. These solutions have also been compared with the unique similar work at the state of the art, revealing to be beneficial under certain constraints. Moreover, the proposed approach has been generalized with some guidelines helpful to designers facing similar problems

A Reconfigurable Digital Multiplier and 4:2 Compressor Cells Design

With the continually growing use of portable computing devices and increasingly complex software applications, there is a constant push for low power high speed circuitry to support this technology. Because of the high usage and large complex circuitry required to carry out arithmetic operations used in applications such as digital signal processing, there has been a great focus on increasing the efficiency of computer arithmetic circuitry. A key player in the realm of computer arithmetic is the digital multiplier and because of its size and power consumption, it has moved to the forefront of today\u27s research. A digital reconfigurable multiplier architecture will be introduced. Regulated by a 2-bit control signal, the multiplier is capable of double and single precision multiplication, as well as fault tolerant and dual throughput single precision execution. The architecture proposed in this thesis is centered on a recursive multiplication algorithm, where a large multiplication is carried out using recursions of simpler submultiplier modules. Within each sub-multiplier module, instead of carry save adder arrays, 4:2 compressor rows are utilized for partial product reduction, which present greater efficiency, thus result in lower delay and power consumption of the whole multiplier. In addition, a study of various digital logic circuit styles are initially presented, and then three different designs of 4:2 compressor in Domino Logic are presented and simulation results confirm the property of proposed design in terms of delay, power consumption and operation frequenc

Reconfigurable RF Energy Harvester with Customized Differential PCB Antenna

In this work, a RF Energy harvester comprised of a differential RF-DC CMOS converter realized in ST130nm CMOS technology and a customized broadband PCB antenna with inductive coupling feeding is presented. Experimental results show that the system can work with different carrier frequencies and thanks to its reconfigurable architecture the proposed converter is able to provide a regulated output voltage of 2 V over a 14 dB of RF input power range. The conversion efficiency of the whole system peaks at 18% under normal outdoor working conditions