Design of a tunable multi-band differential LC VCO using 0.35 mu m SiGe BiCMOS technology for multi-standard wireless communication systems

In this paper, an integrated 2.2-5.7GHz multi-band differential LC VCO for multi-standard wireless communication systems was designed utilizing 0.35 mu m SiGe BiCMOS technology. The topology, which combines the switching inductors and capacitors together in the same circuit, is a novel approach for wideband VCOs. Based on the post-layout simulation results, the VCO can be tuned using a DC voltage of 0 to 3.3 V for 5 different frequency bands (2.27-2.51 GHz, 2.48-2.78 GHz, 3.22-3.53 GHz, 3.48-3.91 GHz and 4.528-5.7 GHz) with a maximum bandwidth of 1.36 GHz and a minimum bandwidth of 300 MHz. The designed and simulated VCO can generate a differential output power between 0.992 and -6.087 dBm with an average power consumption of 44.21 mW including the buffers. The average second and third harmonics level were obtained as -37.21 and -47.6 dBm, respectively. The phase noise between -110.45 and -122.5 dBc/Hz, that was simulated at 1 MHz offset, can be obtained through the frequency of interest. Additionally, the figure of merit (FOM), that includes all important parameters such as the phase noise, the power consumption and the ratio of the operating frequency to the offset frequency, is between -176.48 and -181.16 and comparable or better than the ones with the other current VCOs. The main advantage of this study in comparison with the other VCOs, is covering 5 frequency bands starting from 2.27 up to 5.76 GHz without FOM and area abandonment. Output power of the fundamental frequency changes between -6.087 and 0.992 dBm, depending on the bias conditions (operating bands). Based on the post-layout simulation results, the core VCO circuit draws a current between 2.4-6.3 mA and between 11.4 and 15.3 mA with the buffer circuit from 3.3 V supply. The circuit occupies an area of 1.477 mm(2) on Si substrate, including DC, digital and RF pads

Realization of a voltage controlled oscillator using 0.35 um sige-bicmos technology for multi-band applications

The stable growth in wireless communications market has engendered the interoperability of various standards in a single broadband frequency range from hundred MHz up to several GHz. This frequency range consists of various wireless applications such as GSM, Bluetooth and WLAN. Therefore, an agile wireless system needs smart RF front-ends for functioning properly in such a crowded spectrum. As a result, the demand for multi-standard RF transceivers which put various wireless and cordless phone standards together in one structure was increased. The demand for multi-standard RF transceivers gives a key role to reconfigurable wideband VCO operation with low-power and low-phase noise characteristics. Besides agility and intelligence, such a communication system (GSM, WLAN, Global Positioning Systems, etc. ) required meeting the requirements of several standards in a cost-effective way. This, when cost and integration are the major concerns, leads to the exploitation of Si-based technologies. In this thesis, an integrated 2.2-5.7GHz Multi-band differential LC VCO for Multi-standard Wireless Communication systems was designed utilizing 0.35μm SiGe BiCMOS technology. The topology, which combines the switching inductors and capacitors together in the same circuit, is a novel approach for wideband VCOs. Based on the post layout simulation results, the VCO can be tuned using a DC voltage of 0 to 3.3V for 5 different frequency bands (2.27-2.51 GHz, 2.48-2.78GHz, 3.22-3.53GHz, 3.48-3.91GHz and 4.528-5.7GHz) with a maximum bandwidth of 1.36GHz and a minimum bandwidth of 300MHz. The designed and simulated VCO can generate a differential output power between 0.992 dBm and -6.087 dBm with an average power consumption of 44.21mW including the buffers. The average second and third harmonics level were obtained as -37.21 dBm and -47.6 dBm, respectively. The phase noise between -110.45 and -122.5 dBc/Hz, that was simulated at 1 MHz offset, can be obtained through the frequency of interest. Additionally, the figure of merit (FOM), that includes all important parameters such as the phase noise, the power consumption and the ratio of the operating frequency to the offset frequency, is between -176.48 and -181.16 and comparable or better than the ones with the other current VCOs. The main advantage of this study in comparison with the other VCOs, is covering 5 frequency bands starting from 2.27 up to 5.76 GHz without FOM and area abandonment

A Fully Differential Phase-Locked Loop With Reduced Loop Bandwidth Variation

Phase-Locked Loops (PLLs) are essential building blocks to wireless communications as they are responsible for implementing the frequency synthesizer within a wireless transceiver. In order to maintain the rapid pace of development thus far seen in wireless technology, the PLL must develop accordingly to meet the increasingly demanding requirements imposed on it by today's (and tomorrows) wireless devices. Specically this entails meeting stringent noise specications imposed by modern wireless standards, meeting low power consumption budgets to prolong battery lifetimes, operating under reduced supply voltages imposed by modern technology nodes and within the noisy environments of complex system-on-chip (SOC) designs, all in addition to consuming as little silicon area as possible. The ability of the PLL to achieve the above is thus key to its continual progress in enabling wireless technology achieve increasingly powerful products which increasingly benet our daily lives. This thesis furthers the development of PLLs with respect to meeting the challenges imposed upon it by modern wireless technology, in two ways. Firstly, the thesis describes in detail the advantages to be gained through employing a fully dierential PLL. Specically, such PLLs are shown to achieve low noise performance, consume less silicon area than their conventional counterparts whilst consuming similar power, and being better suited to the low supply voltages imposed by continual technology downsizing. Secondly, the thesis proposes a sub-banded VCO architecture which, in addition to satisfying simultaneous requirements for large tuning ranges and low phase noise, achieves signicant reductions in PLL loop bandwidth variation. First and foremost, this improves on the stability of the PLL in addition to improving its dynamic locking behaviour whilst oering further improvements in overall noise performance. Since the proposed sub-banded architecture requires no additional power over a conventional sub-banded architecture, the solution thus remains attractive to the realm of low power design. These two developments combine to form a fully dierential PLL with reduced loop bandwidth variation. As such, the resulting PLL is well suited to meeting the increasingly demanding requirements imposed on it by today's (and tomorrows) wireless devices, and thus applicable to the continual development of wireless technology in benetting our daily lives

Analysis and design of wideband voltage controlled oscillators using self-oscillating active inductors.

Voltage controlled oscillators (VCOs) are essential components of RF circuits used in transmitters and receivers as sources of carrier waves with variable frequencies. This, together with a rapid development of microelectronic circuits, led to an extensive research on integrated implementations of the oscillator circuits. One of the known approaches to oscillator design employs resonators with active inductors electronic circuits simulating the behavior of passive inductors using only transistors and capacitors. Such resonators occupy only a fraction of the silicon area necessary for a passive inductor, and thus allow to use chip area more eectively. The downsides of the active inductor approach include: power consumption and noise introduced by transistors. This thesis presents a new approach to active inductor oscillator design using selfoscillating active inductor circuits. The instability necessary to start oscillations is provided by the use of a passive RC network rather than a power consuming external circuit employed in the standard oscillator approach. As a result, total power consumption of the oscillator is improved. Although, some of the active inductors with RC circuits has been reported in the literature, there has been no attempt to utilise this technique in wideband voltage controlled oscillator design. For this reason, the dissertation presents a thorough investigation of self-oscillating active inductor circuits, providing a new set of design rules and related trade-os. This includes: a complete small signal model of the oscillator, sensitivity analysis, large signal behavior of the circuit and phase noise model. The presented theory is conrmed by extensive simulations of wideband CMOS VCO circuit for various temperatures and process variations. The obtained results prove that active inductor oscillator performance is obtained without the use of standard active compensation circuits. Finally, the concept of self-oscillating active inductor has been employed to simple and fast OOK (On-Off Keying) transmitter showing energy eciency comparable to the state of the art implementations reported in the literature

Advanced CMOS Integrated Circuit Design and Application

The recent development of various application systems and platforms, such as 5G, B5G, 6G, and IoT, is based on the advancement of CMOS integrated circuit (IC) technology that enables them to implement high-performance chipsets. In addition to development in the traditional fields of analog and digital integrated circuits, the development of CMOS IC design and application in high-power and high-frequency operations, which was previously thought to be possible only with compound semiconductor technology, is a core technology that drives rapid industrial development. This book aims to highlight advances in all aspects of CMOS integrated circuit design and applications without discriminating between different operating frequencies, output powers, and the analog/digital domains. Specific topics in the book include: Next-generation CMOS circuit design and application; CMOS RF/microwave/millimeter-wave/terahertz-wave integrated circuits and systems; CMOS integrated circuits specially used for wireless or wired systems and applications such as converters, sensors, interfaces, frequency synthesizers/generators/rectifiers, and so on; Algorithm and signal-processing methods to improve the performance of CMOS circuits and systems

Analysis and design of a 195.6 dBc/Hz peak FoM P-N class-B oscillator with transformer-based tail filtering

A complementary p-n class-B oscillator with two magnetically coupled second harmonic tail resonators is presented and compared to an N-only reference one. An in depth analysis of phase noise, based on direct derivation of the Impulse Sensitivity Function (ISF), provides design insights on the optimization of the tail resonators. In principle the complementary p-n oscillator has the same optimum Figure of Merit (FoM) of the N-only at half the voltage swing. At a supply voltage of 1.5 V, the maximum allowed oscillation amplitude of the N-only is constrained, by reliability considerations, to be smaller than the value that corresponds to the optimum FoM even when 1.8 V thick oxide transistors are used. For an oscillation amplitude that ensures reliable operation and the same tank, the p-n oscillator achieves a FoM 2 to 3 dB better than the N, only depending on the safety margin taken in the design. After frequency division by 2, the p-n oscillator has a measured phase noise that ranges from -150.8 to -151.5 dBc/Hz at 10 MHz offset from the carrier when the frequency of oscillation is varied from 7.35 to 8.4 GHz. With a power consumption of 6.3 mW, a peak FoM of 195.6 dBc/Hz is achieved.This work was supported by the European Marie Curie IAPP Grant Agreement N 251399.info:eu-repo/semantics/publishedVersio

Design Of A 2.4 Ghz Low Power Lc Vco In Umc 0.18u Technology

Tez (Yüksek Lisans) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2007Thesis (M.Sc.) -- İstanbul Technical University, Institute of Science and Technology, 2007Bu çalışmada, Bluetooth uygulamalarında kullanılmak üzere 2.45GHz merkez frekansında çalışan, frekans ayarlaması 2.2GHz ile 2.7GHz arasında değişen, düşük güç (2mW) tüketimi sağlayan bir LC GKO (VCO) tasarlanmıştır. Faz gürültüsünü minimize etmek maksadıyla 4 bit anahtarlamalı IMOS dizisinden yararlanılmıştır. Ayrıca frekansın ince ayarı için kapasite kuplajlı diyot varaktör devresi eklenmiştir. Bu frekans ayarlama tekniğinin faz gürültüsüne etkisi en kötü hal için 50kHz ofsette yaklaşık olarak 2dBc/Hz olup yüksek ofsetlerde yok denecek kadar azdır. Devrenin kaba kontrol gerilimleri 1.4V ve 0V olup, ince ayar gerilimi ise 0.5V ile 1.4V arasındadır. Besleme geriliminin 1.4V olduğu dikkate alındığında devre yüksek entegrasyon olanağı sunmaktadır. Faz gürültüsü 50kHz ofsette -88.6dBc/Hz ile -94.36dBc/Hz arasında olup 3MHz ofsette ise -128.3dBc/Hz ile -130.5dBc/Hz değerlerine ulaşmaktadır.Bu devreye ek olarak daha düşük gerilimli farklı topolojiler aynı akım akıtacak şekilde tasarlanmış ve tezin aynı zamanda ISM bandında çalışan düşük güç sarfiyatı isteyen uygulamalarda gerekli olacak bir GKO ihtiyacı için karşılaştırmalı bir çalışma olması sağlanmıştır.In this study, a low power LC VCO which operates at a center frequency of 2.45GHz over the range between 2.2GHz and 2.7GHz is designed for Bluetooth applications. The oscillator consumes 2mW at a supply voltage of 1.4V. To minimize the phase noise generated by the varactor through AM-PM conversion, 4bits SCA varactor is implemented by employing IMOS varactors. For fine tuning of frequency, a capacitor coupled diode varactor structure is designed. The effect of this overall varactor structure on the phase noise is around 2dBc/Hz at 50kHz offset for the worst case whereas it is negligble at high offsets. The coarse control tuning voltage values are 0V and 1.4V and the fine tuning control voltage varies from 0.5V to 1.4V. Hence, a high integration is achieved by keeping the external voltage at power supply voltage. The phase noise is between -88.6dBc/Hz and -94.36dBc/Hz at 50kHz offset, and between -128.3dBc/Hz and -130.5dBc/Hz at 3MHz offset. In addition to this, several circuits enabling lower supply voltage are simulated by keeping the same current in order to constitute a comparative study for low power applications which do not require stringent phase noise specification at 2.4GHz.Yüksek LisansM.Sc

Capacitance to voltage converter design for biosensor applications

Due to advances in MEMS fabrication, Lab-on-Chip (LoC) technology gained great progress. LoC refers to small chips that might do similar works to equipped laboratory. Miniaturization of laboratory platform results in low area, low sampleconsumption and less measurement time. Hence, LoC with IC integration finds numerous implementations in biomedical applications. Electrochemical biosensors are preferred for LoC applications because electrochemical biosensors can be easily integrated into IC designs due to electrode-based transducing. Capacitive biosensors are distinctive in electrochemical biosensors because of their reliability and sensitivity advantages. Therefore Interdigitated electrode (IDE) capacitor based biosensor system is preferred for development of biosensor platform. In this thesis, capacitive biosensor system with new Capacitance to Voltage Converter (CVC) designs for LoC applications is presented. Multiple IDE capacitor sensing and varactor-based compensation are new ideas that are presented in this thesis. Proposed system consists of five blocks; IDE Capacitor based tranducer, CVC, Low-Pass Filter, Linear LC-Tank Voltage Controlled Oscillator (VCO) and Class-E Power Amplifier (PA). System building blocks are designed and fabricated using IHP's 0.25 µm SiGe BiCMOS process because of its advantage at high frequency and post-process that IHP offers. Varactor tunable CVC design provides highly linear relationship between output voltage and capacitance change in sensing capacitor. Varactor is used in reference capacitor to compensate changes in sensing capacitor. Total chip area is 0.4 mm2 including pads. 10 MHz operating frequency is achieved. Total power consumption changes between 441 µW and 1,037 mW depending on the sensor capacitance