Design exploration and performance strategies towards power-efficient FPGA-based achitectures for sound source localization

Many applications rely on MEMS microphone arrays for locating sound sources prior to their execution. Those applications not only are executed under real-time constraints but also are often embedded on low-power devices. These environments become challenging when increasing the number of microphones or requiring dynamic responses. Field-Programmable Gate Arrays (FPGAs) are usually chosen due to their flexibility and computational power. This work intends to guide the design of reconfigurable acoustic beamforming architectures, which are not only able to accurately determine the sound Direction-Of-Arrival (DoA) but also capable to satisfy the most demanding applications in terms of power efficiency. Design considerations of the required operations performing the sound location are discussed and analysed in order to facilitate the elaboration of reconfigurable acoustic beamforming architectures. Performance strategies are proposed and evaluated based on the characteristics of the presented architecture. This power-efficient architecture is compared to a different architecture prioritizing performance in order to reveal the unavoidable design trade-offs

Programmable rate modem utilizing digital signal processing techniques

The engineering development study to follow was written to address the need for a Programmable Rate Digital Satellite Modem capable of supporting both burst and continuous transmission modes with either binary phase shift keying (BPSK) or quadrature phase shift keying (QPSK) modulation. The preferred implementation technique is an all digital one which utilizes as much digital signal processing (DSP) as possible. Here design tradeoffs in each portion of the modulator and demodulator subsystem are outlined, and viable circuit approaches which are easily repeatable, have low implementation losses and have low production costs are identified. The research involved for this study was divided into nine technical papers, each addressing a significant region of concern in a variable rate modem design. Trivial portions and basic support logic designs surrounding the nine major modem blocks were omitted. In brief, the nine topic areas were: (1) Transmit Data Filtering; (2) Transmit Clock Generation; (3) Carrier Synthesizer; (4) Receive AGC; (5) Receive Data Filtering; (6) RF Oscillator Phase Noise; (7) Receive Carrier Selectivity; (8) Carrier Recovery; and (9) Timing Recovery

Signal Encoding and Digital Signal Processing in Continuous Time

This work investigates signal encoding in, and architectures of, digital signal processing systems that function in continuous time (CT). Unlike conventional digital signal processors (DSPs), which rely on a clock to dictate the sampling times of an analog-to-digital converter (ADC) and to provide the tap delay timing, CT DSPs function entirely in continuous time, without a sampling or a synchronizing clock. The samples of a CT DSP system are generated and processed only when some measure of the input signal crosses a predetermined threshold. The effective sampling rate and the dynamic power dissipation of a CT digital system automatically adapt to the activity of the input signal. The properties of signals sampled in continuous time are investigated in this thesis. A technique for reducing the effective sampling rate of a CT system is presented, in which the digital signal encoding is varied by adjusting the resolution according to a property of the input. A variable-resolution system leads to a decrease in the number of samples generated, a reduction in the power dissipation and a reduction in the effective chip area of a CT DSP, all without sacrificing in-band performance. The properties of several asynchronous signal-driven sampling techniques are analyzed and compared. The architecture and signal encoding of CT DSPs for signals in the lower gigahertz frequency range are investigated, with consideration of speed and accuracy limitations in the context of submicron CMOS technologies. A per-edge digital signal encoding technique is developed, which bypasses timing problems of processing high-speed digital signals; the properties of per-edge encoded signals are discussed. The design considerations of a low-resolution per-edge-encoded gigahertz-range CT DSP are discussed and an implementation for a possible application is detailed. A prototype chip has been fabricated in ST 65 nm CMOS technology, which has a compact processor core area of 0.073 mm^2. The implemented CT digital processor achieves SNDR of over 20 dB with 3 bits of resolution and a maximum usable -3 dB bandwidth of 0.8 GHz to 3.2 GHz. The processor can be configured as a one-tap to six-tap CT FIR filter and has an active power dissipation that varies from 0.27 mW to 9.5 mW, depending on the amplitude and frequency of the input signal

On the Energy Efficiency of LT Codes in Proactive Wireless Sensor Networks

This paper presents an in-depth analysis on the energy efficiency of Luby Transform (LT) codes with Frequency Shift Keying (FSK) modulation in a Wireless Sensor Network (WSN) over Rayleigh fading channels with pathloss. We describe a proactive system model according to a flexible duty-cycling mechanism utilized in practical sensor apparatus. The present analysis is based on realistic parameters including the effect of channel bandwidth used in the IEEE 802.15.4 standard, active mode duration and computation energy. A comprehensive analysis, supported by some simulation studies on the probability mass function of the LT code rate and coding gain, shows that among uncoded FSK and various classical channel coding schemes, the optimized LT coded FSK is the most energy-efficient scheme for distance d greater than the pre-determined threshold level d_T , where the optimization is performed over coding and modulation parameters. In addition, although the optimized uncoded FSK outperforms coded schemes for d < d_T , the energy gap between LT coded and uncoded FSK is negligible for d < d_T compared to the other coded schemes. These results come from the flexibility of the LT code to adjust its rate to suit instantaneous channel conditions, and suggest that LT codes are beneficial in practical low-power WSNs with dynamic position sensor nodes.Comment: accepted for publication in IEEE Transactions on Signal Processin

Single-Carrier Modulation versus OFDM for Millimeter-Wave Wireless MIMO

This paper presents results on the achievable spectral efficiency and on the energy efficiency for a wireless multiple-input-multiple-output (MIMO) link operating at millimeter wave frequencies (mmWave) in a typical 5G scenario. Two different single-carrier modem schemes are considered, i.e., a traditional modulation scheme with linear equalization at the receiver, and a single-carrier modulation with cyclic prefix, frequency-domain equalization and FFT-based processing at the receiver; these two schemes are compared with a conventional MIMO-OFDM transceiver structure. Our analysis jointly takes into account the peculiar characteristics of MIMO channels at mmWave frequencies, the use of hybrid (analog-digital) pre-coding and post-coding beamformers, the finite cardinality of the modulation structure, and the non-linear behavior of the transmitter power amplifiers. Our results show that the best performance is achieved by single-carrier modulation with time-domain equalization, which exhibits the smallest loss due to the non-linear distortion, and whose performance can be further improved by using advanced equalization schemes. Results also confirm that performance gets severely degraded when the link length exceeds 90-100 meters and the transmit power falls below 0 dBW.Comment: accepted for publication on IEEE Transactions on Communication

An Efficient Polyphase Filter Based Resampling Method for Unifying the PRFs in SAR Data

Variable and higher pulse repetition frequencies (PRFs) are increasingly being used to meet the stricter requirements and complexities of current airborne and spaceborne synthetic aperture radar (SAR) systems associated with higher resolution and wider area products. POLYPHASE, the proposed resampling scheme, downsamples and unifies variable PRFs within a single look complex (SLC) SAR acquisition and across a repeat pass sequence of acquisitions down to an effective lower PRF. A sparsity condition of the received SAR data ensures that the uniformly resampled data approximates the spectral properties of a decimated densely sampled version of the received SAR data. While experiments conducted with both synthetically generated and real airborne SAR data show that POLYPHASE retains comparable performance to the state-of-the-art BLUI scheme in image quality, a polyphase filter-based implementation of POLYPHASE offers significant computational savings for arbitrary (not necessarily periodic) input PRF variations, thus allowing fully on-board, in-place, and real-time implementation

A mixed-signal integrated circuit for FM-DCSK modulation

This paper presents a mixed-signal application-specific integrated circuit (ASIC) for a frequency-modulated differential chaos shift keying (FM-DCSK) communication system. The chip is conceived to serve as an experimental platform for the evaluation of the FM-DCSK modulation scheme, and includes several programming features toward this goal. The operation of the ASIC is herein illustrated for a data rate of 500 kb/s and a transmission bandwidth in the range of 17 MHz. Using signals acquired from the test platform, bit error rate (BER) estimations of the overall FM-DCSK communication link have been obtained assuming wireless transmission at the 2.4-GHz ISM band. Under all tested propagation conditions, including multipath effects, the system obtains a BER = 10-3 for Eb/No lower than 28 dB.Ministerio de Ciencia y Tecnología TIC2003-0235