Enabling IoT Empowered Smart Lighting Solutions: A Communication Theoretic Perspective

The aim of this article is to explore the design space of the IoT empowered smart lighting systems from communication theoretic perspective. It is noted that traditional wired solution such as digital addressable lighting interface (DALI) need to be replaced altogether. The solutions proposing to replace just the end connections by wireless transceivers will not fit in the emerging IoT paradigm. Different architectural blocks of smart lighting systems are briefly described. The key enablers for each of these blocks, their evolution trajectories, existing challenges and possible pathways are briefly summarized. It is noted that the functionality of the building block of IoT based smart lighting system can be translated into an abstract reference architecture. A hirerichical networking architecture is proposed and different networking issues are discussed. Finally, a communication theoretic perspective for wireless interface selection is presented

Parametric analog signal amplification applied to nanoscale cmos wireless digital transceivers

Thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the subject of Electrical and Computer Engineering by the Universidade Nova de Lisboa,Faculdade de Ciências e TecnologiaSignal amplification is required in almost every analog electronic system. However noise is also present, thus imposing limits to the overall circuit performance, e.g., on the sensitivity of the radio transceiver. This drawback has triggered a major research on the field, which has been producing several solutions to achieve amplification with minimum added noise. During the Fifties, an interesting out of mainstream path was followed which was based on variable reactance instead of resistance based amplifiers. The principle of these parametric circuits permits to achieve low noise amplifiers since the controlled variations of pure reactance elements is intrinsically noiseless. The amplification is based on a mixing effect which enables energy transfer from an AC pump source to other related signal frequencies. While the first implementations of these type of amplifiers were already available at that time, the discrete-time version only became visible more recently. This discrete-time version is a promising technique since it is well adapted to the mainstream nanoscale CMOS technology. The technique itself is based on the principle of changing the surface potential of the MOS device while maintaining the transistor gate in a floating state. In order words, the voltage amplification is achieved by changing the capacitance value while maintaining the total charge unchanged during an amplification phase. Since a parametric amplifier is not intrinsically dependent on the transconductance of the MOS transistor, it does not directly suffer from the intrinsic transconductance MOS gain issues verified in nanoscale MOS technologies. As a consequence, open-loop and opamp free structures can further emerge with this additional contribution. This thesis is dedicated to the analysis of parametric amplification with special emphasis on the MOS discrete-time implementation. The use of the latter is supported on the presentation of several circuits where the MOS Parametric Amplifier cell is well suited: small gain amplifier, comparator, discrete-time mixer and filter, and ADC. Relatively to the latter, a high speed time-interleaved pipeline ADC prototype is implemented in a,standard 130 nm CMOS digital technology from United Microelectronics Corporation (UMC). The ADC is fully based on parametric MOS amplification which means that one could achieve a compact and MOS-only implementation. Furthermore, any high speed opamp has not been used in the signal path, being all the amplification steps implemented with open-loop parametric MOS amplifiers. To the author’s knowledge, this is first reported pipeline ADC that extensively used the parametric amplification concept.Fundação para a Ciência e Tecnologia through the projects SPEED, LEADER and IMPAC

Configurable circuits and their impact on multi-standard RF front-end architectures

This thesis studies configurable circuits and their impact on multi-standard RF front-end architectures. In particular, low-voltage low-power linear LNA and mixer topologies suitable for implementation in multi-standard front-ends are subject of the investigation. With respect to frequency and bandwidth, multi-standard front-ends can be implemented using either tunable or wideband LNA and mixer topologies. Based on the type of the LNA and mixer(s), multi-standard receiver RF front-ends can be divided into three groups. They can be (tunable) narrow-band, wide-band or combined. The advantages and disadvantages of the different multi-standard receiver RF front-ends have been discussed in detail. The partitioning between off-chip selectivity, on-chip selectivity provided by the LNA and mixer, linearity, power consumption and occupied chip area in each multi-standard RF front-end group are thoroughly investigated. A Figure of Merit (FOM) for the multi-standard receiver RF front-end has been introduced. Based on this FOM the most suitable multi-standard RF front-end group in terms of cost-effectiveness can be selected. In order to determine which multi-standard RF front-end group is the most cost-effective for a practical application, a GSM850/E-GSM/DCS/PCS/Bluetooth/WLANa/b/g multi-standard receiver RF front-end is chosen as a demonstrator. These standards are the most frequently used standards in wireless communication, and this combination of standards allows to users almost "anytime-anywhere" voice and data transfer. In order to verify these results, three demonstrators have been defined, designed and implemented, two wideband RF front-end circuits in 90nm CMOS and 65nm CMOS, and one combined multi-standard RF front-end circuit in 65nm CMOS. The proposed multi-standard demonstrators have been compared with the state-of the art narrow-band, wide-band and combined multi-standard RF front-ends. On the proposed multi-standard RF front-ends and the state-of the art multi-standard RF front-ends the proposed FOM have been applied. The comparison shows that the combined multi-standard RF front-end group is the most cost effective multi-standard group for this application

Novel Approaches in RF/Analog CMOS Spectrum Sensing and Its Applications

Real time spectrum sensing refers to searching for possible signals at a specific time and location, which is applicable to cognitive radio (CR) for primary signal detection and ultra-wideband (UWB) radio for interferer detection. There are several approaches for spectrum sensing. Choosing a proper method for spectrum sensing necessitates evaluating several trade-offs among sensing time, accuracy, power consumption and simplicity of implementation. In this dissertation several approaches for spectrum sensing along with the applications to CR and UWB receivers are presented. A novel simple spectrum sensing technique for detecting weak primary signals with negative signal-to-noise ratio (SNR) is proposed, which is called quasi-cyclostationary feature detection (QCFD) technique. Moreover, a simple, reliable, and fast real-time spectrum sensing technique based on phasers, which are dispersive delay structures (DDSs), is proposed. Lastly, a UWB receiver robust to the narrowband (NB) blockers, in the vicinity of UWB frequency, is presented. To increase the robustness of the UWB receiver towards interferers, a dynamic blocker detector, utilizing a phaser-based real time spectrum sensing technique, is employed. The proposed spectrum sensing methods provide the best solutions for the intended applications, considering the trade-offs, compared to the state-of-the-art CMOS spectrum sensors