Synthesis of IDDQ-Testable Circuits: Integrating Built-in Current Sensors

"On-Chip" I_{DDQ} testing by the incorporation of Built-In Current (BIC) sensors has some advantages over "off-chip" techniques. However, the integration of sensors poses analog design problems which are hard to be solved by a digital designer. The automatic incorporation of the sensors using parameterized BIC cells could be a promising alternative. The work reported here identifies partitioning criteria to guide the synthesis of I_{DDQ}-testable circuits. The circuit must be partitioned, such that the defective I_{DDQ} is observable, and the power supply voltage perturbation is within specified limits. In addition to these constraints, also cost criteria are considered: circuit extra delay, area overhead of the BIC sensors, connectivity costs of the test circuitry, and the test application time. The parameters are estimated based on logical as well as electrical level information of the target cell library to be used in the technology mapping phase of the synthesis process. The resulting cost function is optimized by an evolution-based algorithm. When run over large benchmark circuits our method gives significantly superior results to those obtained using simpler and less comprehensive partitioning methods.Postprint (published version

Test and Testability of Asynchronous Circuits

The ever-increasing transistor shrinkage and higher clock frequencies are causing serious clock distribution, power management, and reliability issues. Asynchronous design is predicted to have a significant role in tackling these challenges because of its distributed control mechanism and on-demand, rather than continuous, switching activity. Null Convention Logic (NCL) is a robust and low-power asynchronous paradigm that introduces new challenges to test and testability algorithms because 1) the lack of deterministic timing in NCL complicates the management of test timing, 2) all NCL gates are state-holding and even simple combinational circuits show sequential behaviour, and 3) stuck-at faults on gate internal feedback (GIF) of NCL gates do not always cause an incorrect output and therefore are undetectable by automatic test pattern generation (ATPG) algorithms. Existing test methods for NCL use clocked hardware to control the timing of test. Such test hardware could introduce metastability issues into otherwise highly robust NCL devices. Also, existing test techniques for NCL handle the high-statefulness of NCL circuits by excessive incorporation of test hardware which imposes additional area, propagation delay and power consumption. This work, first, proposes a clockless self-timed ATPG that detects all faults on the gate inputs and a share of the GIF faults with no added design for test (DFT). Then, the efficacy of quiescent current (IDDQ) test for detecting GIF faults undetectable by a DFT-less ATPG is investigated. Finally, asynchronous test hardware, including test points, a scan cell, and an interleaved scan architecture, is proposed for NCL-based circuits. To the extent of our knowledge, this is the first work that develops clockless, self-timed test techniques for NCL while minimising the need for DFT, and also the first work conducted on IDDQ test of NCL. The proposed methods are applied to multiple NCL circuits with up to 2,633 NCL gates (10,000 CMOS Boolean gates), in 180 and 45 nm technologies and show average fault coverage of 88.98% for ATPG alone, 98.52% including IDDQ test, and 99.28% when incorporating test hardware. Given that this fault coverage includes detection of GIF faults, our work has 13% higher fault coverage than previous work. Also, because our proposed clockless test hardware eliminates the need for double-latching, it reduces the average area and delay overhead of previous studies by 32% and 50%, respectively

Sensors i estratègies de test de circuits digitals CMOS per vigilància del consum

El objetivo de la tesis es realizar aportaciones en el campo de las estrategias de test basadas en la vigilancia del consumo quiescente de los circuitos integrados CMOS y de los sensores utilizados para dicho fin (test de corriente o test iddq). Para ello se analiza en primer lugar el estado del arte en el diseño de sensores para el test IDDQ y se extraen criterios para la evaluacion de la calidad de dichos sensores. En la tesis se propone un nuevo tipo de sensor integrado (proportional built-in current sensor) que utiliza como elemento transductor un transistor bipolar compatible con la tecnologia CMOS. Se caracteriza tambien su comportamiento estetico y dinamico y se realizan pruebas con circuitos experimentales para validar los analisis realizados.En la tesis se proponen dos metodos originales para el test IDDQ mediante sensores externos al circuito que se este verificando (cut): el primero se basa en la desconexion de la alimentacion del cut y en la observacion del comportamiento de sus salidas. El segundo metodo se basa en el analisis de la evolucion de la tension en el nodo de alimentacion de un CUT cuando se le aplica un conjunto de vectores de test estando el circuito alimentado por un condensador. Ambos metodos propuestos requieren un interruptor para la alimentacion del CUT con unas caracteristicas especiales. Por ello, se ha diseñado un nuevo tipo de interruptor que cumple con las especificaciones de baja resistencia en estado de conduccion y baja inyeccion de carga en el paso del estado de no conduccion al de conduccion. Finalmente, los metodos propuestos se han validado experimentalmente al ser implementados en una maquina de test convencional verificandose su efectividad en la deteccion de los defectos de multiples circuitos integrados