Operating system for a real-time multiprocessor propulsion system simulator

The success of the Real Time Multiprocessor Operating System (RTMPOS) in the development and evaluation of experimental hardware and software systems for real time interactive simulation of air breathing propulsion systems was evaluated. The Real Time Multiprocessor Operating System (RTMPOS) provides the user with a versatile, interactive means for loading, running, debugging and obtaining results from a multiprocessor based simulator. A front end processor (FEP) serves as the simulator controller and interface between the user and the simulator. These functions are facilitated by the RTMPOS which resides on the FEP. The RTMPOS acts in conjunction with the FEP's manufacturer supplied disk operating system that provides typical utilities like an assembler, linkage editor, text editor, file handling services, etc. Once a simulation is formulated, the RTMPOS provides for engineering level, run time operations such as loading, modifying and specifying computation flow of programs, simulator mode control, data handling and run time monitoring. Run time monitoring is a powerful feature of RTMPOS that allows the user to record all actions taken during a simulation session and to receive advisories from the simulator via the FEP. The RTMPOS is programmed mainly in PASCAL along with some assembly language routines. The RTMPOS software is easily modified to be applicable to hardware from different manufacturers

Temporal constraint reasoning in microprocessor systems diagnosis.

by Yuen Siu Ming.Thesis (M.Phil.)--Chinese University of Hong Kong, 1995.Includes bibliographical references (leaves 104-110).Chapter 1 --- Introduction --- p.1Chapter 2 --- Background --- p.4Chapter 2.1 --- Approaches in Formal Hardware Verification --- p.4Chapter 2.1.1 --- Theorem Proving --- p.5Chapter 2.1.2 --- Symbolic Simulation --- p.5Chapter 2.1.3 --- Model Checking --- p.6Chapter 2.2 --- Temporal Theories --- p.7Chapter 2.3 --- Related Works --- p.8Chapter 2.3.1 --- Consistency and Satisfiability of Timing Specifications --- p.8Chapter 2.3.2 --- Symbolic Constraint Satisfaction --- p.9Chapter 3 --- Problem Domain --- p.11Chapter 3.1 --- Basics of MC68000 Read Cycle --- p.11Chapter 4 --- Knowledge-based System Structure --- p.13Chapter 4.1 --- Diagnostic Reasoning Mechanisms --- p.14Chapter 4.2 --- Occurring Event Sequence --- p.16Chapter 4.3 --- Equivalent Goals --- p.17Chapter 4.4 --- CPU Databus Setup Time --- p.17Chapter 4.5 --- Assertion of CPU AS Signal --- p.19Chapter 5 --- Time Range Approach --- p.21Chapter 5.1 --- Time Range Represent ation --- p.21Chapter 5.2 --- Time Ranges Reasoning Techniques --- p.22Chapter 5.2.1 --- Constraint Satisfaction of Time Ranges --- p.22Chapter 5.2.2 --- Constraint Propagation of Time Ranges --- p.25Chapter 5.3 --- Worst-Case Timing Analysis --- p.28Chapter 5.4 --- System Implementation --- p.29Chapter 5.4.1 --- CPU Databus Setup Time --- p.30Chapter 5.4.2 --- Assertion of CPU AS Signal --- p.36Chapter 5.5 --- Implementation Results --- p.40Chapter 5.5.1 --- CPU Databus Setup Time --- p.40Chapter 5.5.2 --- Assertion of CPU AS Signal --- p.40Chapter 5.6 --- Conclusion --- p.41Chapter 6 --- Fuzzy Time Point Approach --- p.43Chapter 6.1 --- Fuzzy Time Point Models --- p.44Chapter 6.1.1 --- Concept of Fuzzy Numbers --- p.44Chapter 6.1.2 --- Definition of Fuzzy Time Points --- p.45Chapter 6.1.3 --- Semi-bounded Fuzzy Time Points --- p.47Chapter 6.2 --- Fuzzy Time Point Reasoning Techniques --- p.48Chapter 6.2.1 --- Constraint Propagation of Fuzzy Time Points --- p.50Chapter 6.2.2 --- Constraint Satisfaction of Fuzzy Time Points --- p.52Chapter 6.3 --- System Implementation --- p.55Chapter 6.3.1 --- Representation of Fuzzy Time Point --- p.55Chapter 6.3.2 --- Fuzzy Time Point Satisfaction --- p.56Chapter 6.3.3 --- Fuzzy Time Point Propagation --- p.58Chapter 6.4 --- Implementation Results --- p.64Chapter 6.4.1 --- CPU Databus Setup Time --- p.64Chapter 6.4.2 --- Assertion of CPU AS Signal --- p.65Chapter 6.5 --- Fuzzy Time Point Model Parameters --- p.66Chapter 6.5.1 --- Variation of Semi-bounded ftps' Membership Function --- p.66Chapter 6.5.2 --- Variation of μftp --- p.67Chapter 6.5.3 --- Variation of K --- p.69Chapter 6.6 --- Conclusion --- p.69Chapter 7 --- Constraint Compatibility Reasoning --- p.72Chapter 7.1 --- Abstract Timing Parameters --- p.73Chapter 7.2 --- MC68000 Read Cycle: Wait States Insertion --- p.75Chapter 7.3 --- Constraint Compatibility of Fuzzy Time Point --- p.75Chapter 7.3.1 --- Crisp Threshold Value --- p.77Chapter 7.3.2 --- Possibility Quantification for the Number of Wait States --- p.78Chapter 7.3.3 --- Threshold Beyond Fuzzy Time Point --- p.80Chapter 7.3.4 --- Fuzzy Time Point Beyond Threshold --- p.80Chapter 7.3.5 --- Threshold Within Fuzzy Time Point --- p.82Chapter 7.4 --- Determine When CPU Clock State is S5 --- p.83Chapter 7.5 --- System Implementation --- p.84Chapter 7.5.1 --- Expert's Heuristic Rule --- p.84Chapter 7.5.2 --- Constraint Compatibility --- p.85Chapter 7.5.3 --- Wait States Insertion --- p.87Chapter 7.6 --- Implementation Results --- p.91Chapter 7.7 --- Conclusion --- p.93Chapter 8 --- Conclusion --- p.95Chapter 8.1 --- Applications in Other Domains --- p.97Chapter 8.2 --- Future Directions and Recommendations --- p.98Chapter A --- Constraint Compatibility Reasoning Output --- p.99Chapter A.1 --- No Wait Cycle Insertion --- p.99Chapter A.2 --- Single Wait Cycle Insertion --- p.100Chapter A.3 --- Two Wait Cycle Insertions --- p.100Chapter B --- MC68020 Read Cycle Problem --- p.101Chapter B.1 --- Basics of MC68020 Read Cycle --- p.101Chapter B.2 --- MC68020 Databus Setup Time --- p.102Chapter B.3 --- Implementation Results --- p.103Bibliography --- p.10

The integrity of serial data highway systems

The Admiralty Surface Weapons Establishment (ASWE) have developed a Local Area Network System. This thesis describes the development of a replacement for this LAN system, based around 16 bit microprocessor hosts, as opposed to the minicomputers currently used. This change gave a substantial reduction in size, and allowed the new system to be installed on a ship and tested under operational conditions. Analysis of the data collected during the tests gave performance information on the ASWE system. The performance of this LAN is compared to that of other leading types of LAN. The design of a portable network controller/ monitor unit is presented, which may be manufactured as a standard controller for the ASWE Serial Highway

Enhanced performance simulation of diesel engines

SIGLEAvailable from British Library Document Supply Centre- DSC:DX90577 / BLDSC - British Library Document Supply CentreGBUnited Kingdo

A cambridge ring node controller

This report gives a discussion of the design of a peripheral controller chip to Interface a Cambridge Ring Node to a MC68000 host machine using VLSI technology. The design of such a chip involves following a design strategy. The strategy used Identities what the Interface should be capable of doing. developing a functional description of the interface. mapping the interface onto silicon and finally verifying the design. The characteristics of the interface and the design strategy. along with the software used In the design. will be discussed

A Parallel Processor System for Nuclear Shell-Model Calculations

This thesis describes the design and implementation of a dedicated parallel processor system for nuclear shell-model calculations. The purpose of these calculations is to determine nuclear energy eigenvalues by the tridiagonalisation of the nuclear Hamiltonian matrix using the Lanczos method. The Theoretical Nuclear Structure group at Glasgow University's Physics Department would normally perform this type of calculation on a high-performance main-frame computer. However these machines have limitations which restrict the number and scope of the calculations that can be performed. The Shell Model Processor system consists of a Multiple Microprocessor Unit (MMPU) driven by a highly pipelined dedicated front-end processor. The MMPU has a modular, moderately coupled, MIMD architecture based on autonomous processing modules. The elements within the system communicate via three shared buses. The front-end is responsible for determining the position of non-zero elements within the Hamiltonian matrix. Once the position of an element has been found it is passed to one of the free processing modules within the MMPU. The processing module then determines the value of the matrix element and performs the appropriate arithmetic to accumulate the resultant Lanczos vector. Two such processing modules have been developed. The most recently developed module is based on two MC68000 16/32 bit microprocessors. In addition there are two supervisory processor modules, one of which controls the front-end and also assists it in its function. The other module has privileged system capabilities and is responsible for supervising the system as a whole. The system has been successfully tested and performance figures are presented. The future expansion of the system to allow it to perform larger calculations is also discussed