Design of Ternary Logic and Arithmetic Circuits Using GNRFET

Multiple valued logic (MVL) can represent an exponentially higher number of data/information compared to the binary logic for the same number of logic bits. Compared to the conventional and other emerging device technologies, Graphene Nano Ribbon Field Effect Transistor (GNRFET) appears to be very promising for designing MVL logic gates and arithmetic circuits due to some exceptional electrical properties of the GNRFET, e.g., the ability to control the threshold voltage by changing the width of the GNR. Variation of the threshold voltage is one of the prescribed techniques to achieve multiple voltage levels to implement the MVL circuit. This paper introduces a design approach for ternary logic gates and circuits using MOS-type GNRFET. The designs of basic ternary logic gates like inverters, NAND, NOR, and ternary arithmetic circuits like the ternary decoder, 3:1 multiplexer, and ternary half-adder are demonstrated using GNRFET. A comparative analysis of the GNRFET based ternary logic gates and circuits and those based on the conventional CMOS and CNTFET technologies is performed using delay, total power, and power-delay-product (PDP) as the metrics. The simulation and analysis are performed using the H-SPICE tool with a GNRFET model available on the Nanohub website

Variability and reliability analysis of carbon nanotube technology in the presence of manufacturing imperfections

In 1925, Lilienfeld patented the basic principle of field effect transistor (FET). Thirty-four years later, Kahng and Atalla invented the MOSFET. Since that time, it has become the most widely used type of transistor in Integrated Circuits (ICs) and then the most important device in the electronics industry. Progress in the field for at least the last 40 years has followed an exponential behavior in accordance with Moore¿s Law. That is, in order to achieve higher densities and performance at lower power consumption, MOS devices have been scaled down. But this aggressive scaling down of the physical dimensions of MOSFETs has required the introduction of a wide variety of innovative factors to ensure that they could still be properly manufactured. Transistors have expe- rienced an amazing journey in the last 10 years starting with strained channel CMOS transistors at 90nm, carrying on the introduction of the high-k/metal-gate silicon CMOS transistors at 45nm until the use of the multiple-gate transistor architectures at 22nm and at recently achieved 14nm technology node. But, what technology will be able to produce sub-10nm transistors? Different novel materials and devices are being investigated. As an extension and enhancement to current MOSFETs some promising devices are n-type III-V and p-type Germanium FETs, Nanowire and Tunnel FETs, Graphene FETs and Carbon Nanotube FETs. Also, non-conventional FETs and other charge-based information carrier devices and alternative information processing devices are being studied. This thesis is focused on carbon nanotube technology as a possible option for sub-10nm transistors. In recent years, carbon nanotubes (CNTs) have been attracting considerable attention in the field of nanotechnology. They are considered to be a promising substitute for silicon channel because of their small size, unusual geometry (1D structure), and extraordinary electronic properties, including excellent carrier mobility and quasi-ballistic transport. In the same way, carbon nanotube field-effect transistors (CNFETs) could be potential substitutes for MOSFETs. Ideal CNFETs (meaning all CNTs in the transistor behave as semiconductors, have the same diameter and doping level, and are aligned and well-positioned) are predicted to be 5x faster than silicon CMOS, while consuming the same power. However, nowadays CNFETs are also affected by manufacturing variability, and several significant challenges must be overcome before these benefits can be achieved. Certain CNFET manufacturing imperfections, such as CNT diameter and doping variations, mispositioned and misaligned CNTs, high metal-CNT contact resistance, the presence of metallic CNTs (m-CNTs), and CNT density variations, can affect CNFET performance and reliability and must be addressed. The main objective of this thesis is to analyze the impact of the current CNFET manufacturing challenges on multi-channel CNFET performance from the point of view of variability and reliability and at different levels, device and circuit level. Assuming that CNFETs are not ideal or non-homogeneous because of today CNFET manufacturing imperfections, we propose a methodology of analysis that based on a CNFET ideal compact model is able to simulate heterogeneous or non-ideal CNFETs; that is, transistors with different number of tubes that have different diameters, are not uniformly spaced, have different source/drain doping levels, and, most importantly, are made up not only of semiconducting CNTs but also metallic ones. This method will allow us to analyze how CNT-specific variations affect CNFET device characteristics and parameters and CNFET digital circuit performance. Furthermore, we also derive a CNFET failure model and propose an alternative technique based on fault-tolerant architectures to deal with the presence of m-CNTs, one of the main causes of failure in CNFET circuits

New Logic Synthesis As Nanotechnology Enabler (invited paper)

Nanoelectronics comprises a variety of devices whose electrical properties are more complex as compared to CMOS, thus enabling new computational paradigms. The potentially large space for innovation has to be explored in the search for technologies that can support large-scale and high- performance circuit design. Within this space, we analyze a set of emerging technologies characterized by a similar computational abstraction at the design level, i.e., a binary comparator or a majority voter. We demonstrate that new logic synthesis techniques, natively supporting this abstraction, are the technology enablers. We describe models and data-structures for logic design using emerging technologies and we show results of applying new synthesis algorithms and tools. We conclude that new logic synthesis methods are required to both evaluate emerging technologies and to achieve the best results in terms of area, power and performance

DESIGN OF MULTI-VALUED LOGIC CELLS USING SINGLE-ELECTRON DEVICES

This thesis proposes a new single-electron tunneling based NDC block and develops an analytical model which can be used for related circuit designs and/or their performance optimization. A piece-wise model is used to describe the I-V characteristics of the proposed NDC block. Four applications based on this NDC block are proposed: (1) Multiple-valued logic static memory cell (2) Schmitt trigger (3) Three-stage ring oscillator (4) ternary full adder using hybrid single-electron transistor and MOS technology. Simulation was done using Cadence Spectre simulator with 180nnm CMOS model and SET MIB macro mode to estimate the performance

프로그램 가능한 하부 전극 어레이 구조를 갖는 고효율 재구성 가능 소자

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 8. 이종호.본 논문에서는 비 휘발성 메모리 (NVM) 기능을 갖는 프로그램 가능한 하부 전극 어레이 (Bottom gate array) 로 구성된 새로운 폴리 실리콘 재구성 가능 소자를 최초로 고안하고 제작 및 분석하였다. 제안된 소자는 소자의 크기, 신뢰성, 균일성 및 재현성 측면에서 매우 효율적이다. 하부 전극 어레이에 직접 바이어스를 인가하거나, 또는 하부 전극의 프로그램/이레이즈 상태를 변화 시킴으로써, 제안된 재구성가능 소자는 n-/p-MOSFET, n-p/p-n 다이오드 중 하나의 형태로 동작할 수 있다. 또한, 소자의 MOSFET 동작에서, 문턱 전압 (Vth)과 접합 저항 (RC)은 하부 전극에 의해 독립적으로 제어 가능하며 이는 제안된 재구성 가능 소자의 고유한 장점이다. 제작된 소자는 n-/p-MOSFET 동작에서 기존의 폴리 실리콘 채널 기반 소자들과 유사한 약 120mV/dec 의 역치하 기울기 (subthreshold swing, SS) 및 106 이상의 on/off 전류 비 특성을 갖는다. 두 개의 동일한 재구성 가능 소자를 이용하여 제작된 풀 스윙 CMOS 인버터 로직 게이트의 동작도 성공적으로 구현되었다. 제작된 소자의 DC I-V 특성, 드레인 전류의 온도 의존성 및 저주파 잡음 특성 측정을 통하여, 하부 전극 전압과 채널 저항 및 쇼트키 접합 저항의 관계를 연구하였다. 이를 통하여 알루미늄 소스/드레인은 n 혹은 p 형으로 전기적으로 도핑된 폴리 실리콘 채널과 쇼트키 접합을 형성하게 되고, 소자의 전류는 쇼트키 역방향 접합 터널링에 의하여 결정됨을 확인하였다. 제작된 소자에 대한 분석을 바탕으로 소자의 제작 공정 최적화를 진행하였으며, 제작 공정 최적화를 통하여 개선된 균일성과 평탄도를 갖는 안정된 하부 전극 구조를 구현하였고 이를 통해 개선된 프로그램/이레이즈 성능과 온 커런트의 증가를 확인하였다. 최적화된 소자의 역치하 기울기는 이중 게이트 동작에서 약 90 mV/dec 로 게이트 제어력이 향상되었고, on/off 전류비는 107 이상으로 증가하였다. 공정 최적화를 통해 각각의 소자를 완전히 격리 시킴으로써, 네 개의 동일한 재구성 가능 소자를 이용하여 제작된 NAND/NOR 로직 게이트의 동작 또한 성공적으로 구현하였다. 또한, 실험과 시뮬레이션을 통하여 소스/드레인 메탈의 종류와 게이트 스택의 전기적 두께가 소자의 특성에 미치는 영향에 대해서도 분석 하였다.A novel poly-Si reconfigurable device with programmable bottom gate array having non-volatile memory (NVM) functionality was demonstrated for the first time. The device is very efficient in terms of device size, reliability, uniformity, and reproducibility. By changing bias or program/erase state (PGM/ERS) of the bottom gates (BGs), a device can be transformed to behave one of the following devices: n-/p-MOSFET, n-p, and p-n diode. Threshold voltage (Vth) and contact resistance (Rc) of MOSFETs can be controlled independently by the BGs. The subthreshold swing (SS) and Ion/Ioff of the n-/p-MOSFETs are ~120 mV/dec and >106, respectively, which are comparable to those of conventional poly-Si devices. Full-swing CMOS inverter logic gates implemented by using two identical reconfigurable devices were successfully demonstrated. Relationship between bottom gate biases and resistance of channel and Schottky junction was investigated by DC I-V, temperature dependency of ID, and low frequency noise measurement. Aluminum source/drain (S/D) layer forms Schottky junction with poly-Si body being electrically doped with n- or p-type, and the current mechanism is dominated by Schottky reverse junction tunneling. Optimization of fabrication process was performed and stable BG structure with enhanced uniformity and flatness was achieved. The optimized device demonstrated enhanced PGM/ERS performance and improved on-current characteristics. Gate controllability was also enhanced in the double gate operation with SS of ~90 mV/dec, and Ion/Ioff increased to more than 107. A full-swing CMOS inverter and NAND/NOR logic gates implemented by using four identical reconfigurable devices were also successfully demonstrated with complete device isolation by process optimization. The effect of S/D metal and electrical oxide thickness (EOT) of the gate stack on the device characteristics were investigated by both experiments and simulations.Chapter 1.Introduction 1 1.1 Motivation 1 1.2 Background of Reconfigurable Devices 9 1.3 Thesis Organization 16 Chapter 2.Proposed Reconfigurable Device 18 2.1 Structure and Features of Proposed Reconfigurable Device 18 2.2 Fundamentals of Proposed Reconfigurable Device 24 Chapter 3.Fabrication of Proposed Reconfigurable Device 30 3.1 Mask Layout and Fabrication Issues 30 3.2 Bottom Gate Formation 38 3.2.1 Nitride Spacer Method. 38 3.2.2 Poly-Si CMP Method 42 3.3 Overall Fabrication Process 47 Chapter 4.Characterization of Proposed Reconfigurable Device 55 4.1 I-V Characteristics of n- and p-MOSFETs 55 4.2 MOSFET I-V with PGM/ERS State of Bottom Gates 61 4.3 p-n / n-p diode operations 67 4.4 Logic Gate Operations 72 Chapter 5.Analysis of Schottky Contact Resistance 75 5.1 Schottky barrier modulation by bottom gate bias 75 5.2 Temperature Dependence of Reconfigurable Device 81 5.3 Noise characteristics of MOSFET with bottom gate biases 84 Chapter 6.Process Optimization and On-current Improvement 87 6.1 Performance of Proposed Device 87 6.2 Process Optimization 89 6.2.1 SiO2 fin Method 89 6.2.2 Enhanced I-V characteristics 96 6.3 On-current Improvement 102 Chapter 7.Conclusions 105 Bibliography 108 Abstract in Korean 116Docto