Design and implementation of a soft-decision decoder for Cortex codes

International audienceCortex codes are a family of rate-1/2 self-dual systematic linear block codes with good distance properties. This paper investigates the challenging issue of designing an efficient soft-decision decoder for Cortex codes. A dedicated algorithm is introduced that takes advantage of the particular structure of the code to simplify the decoding. Simulation results show that the proposed algorithm achieves an excellent trade-off between performance and complexity for short Cortex codes. A decoder architecture for the (32,16,8) Cortex code based on the (4,2,2) Hadamard code has been successfully designed and implemented on FPGA device. To our knowledge, this is the first efficient digital implementation of a soft-decision Cortex decoder

Reed-Solomon turbo product codes for optical communications: from code optimization to decoder design

International audienceTurbo product codes (TPCs) are an attractive solution to improve link budgets and reduce systems costs by relaxing the requirements on expensive optical devices in high capacity optical transport systems. In this paper, we investigate the use of Reed-Solomon (RS) turbo product codes for 40 Gbps transmission over optical transport networks and 10 Gbps transmission over passive optical networks. An algorithmic study is first performed in order to design RS TPCs that are compatible with the performance requirements imposed by the two applications. Then, a novel ultrahigh-speed parallel architecture for turbo decoding of product codes is described. A comparison with binary Bose-Chaudhuri-Hocquenghem (BCH) TPCs is performed. The results show that high-rate RS TPCs offer a better complexity/performance tradeoff than BCH TPCs for low-cost Gbps fiber optic communications

A Universal Receiver for Uplink NOMA Systems

Given its capability in efficient radio resource sharing, non-orthogonal multiple access (NOMA) has been identified as a promising technology in 5G to improve the system capacity, user connectivity, and scheduling latency. A dozen of uplink NOMA schemes have been proposed recently and this paper considers the design of a universal receiver suitable for all potential designs of NOMA schemes. Firstly, a general turbo-like iterative receiver structure is introduced, under which, a universal expectation propagation algorithm (EPA) detector with hybrid parallel interference cancellation (PIC) is proposed (EPA in short). Link-level simulations show that the proposed EPA receiver can achieve superior block error rate (BLER) performance with implementation friendly complexity and fast convergence, and is always better than the traditional codeword level MMSE-PIC receiver for various kinds of NOMA schemes.Comment: This paper has been accepted by IEEE/CIC International Conference on Communications in China (ICCC 2018). 5 pages, 4 figure

Configurable LDPC Decoder Architecture for Regular and Irregular Codes

Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates with excellent quality of service. This paper presents two novel flexible decoder architectures. The first one supports (3, 6) regular codes of rate 1/2 that can be used for different block lengths. The second decoder is more general and supports both regular and irregular LDPC codes with twelve combinations of code lengths −648, 1296, 1944-bits and code rates-1/2, 2/3, 3/4, 5/6- based on the IEEE 802.11n standard. All codes correspond to a block-structured parity check matrix, in which the sub-blocks are either a shifted identity matrix or a zero matrix. Prototype architectures for both LDPC decoders have been implemented and tested on a Xilinx field programmable gate array.NokiaNational Science Foundatio

Secured Audio Signal Transmission in 5G Compatible mmWave Massive MIMO FBMC System with Implementation of Audio-to-image Transformation Aided Encryption Scheme

In this paper, we have made comprehensive study for the performance evaluation of mmWave massive MIMO FBMC wireless communication system. The 165F2;56 large MIMO antenna configured simulated system under investigation incorporates three modern channel coding (Turbo, LDPC and (3, 2) SPC, higher order digital modulation (256-QAM)) and various signal detection (Q-Less QR, Lattice Reduction(LR) based Zero-forcing(ZF), Lattice Reduction (LR) based ZF-SIC and Complex-valued LLL(CLLL) algorithm implemented ZF-SIC) schemes. An audio to image conversion aided chaos-based physical layer security scheme has also been implemented in such study. On considering transmission of encrypted audio signal in a hostile fading channel, it is noticeable from MATLAB based simulation study that the LDPC Channel encoded system is very much robust and effective in retrieving color image under utilization of Lattice Reduction(LR) based ZF-SIC signal detection and 16- QAM digital modulation techniques

New architecture for high data rate turbo decoding of product codes

International audienceThis paper presents a new circuit architecture for turbo decoding, which achieves very high data rates when using product codes as error correcting codes. Although this architecture is independent of the elementary code (convolutional or block) used and of the corresponding decoding algorithms, we focus here on the case of product codes. This innovative circuit architecture stores several data at the same adress and performs parallel decoding to increase the data rate. It is able to process several date simultaneously with one memory (classical designs require m memories); its latency decreases when the amont of data processed simultaneously is large. We present results on block turbo decoder designs of 2-data, 4-date and 8-data decoders (where 2, 4 and 8 are the number of data symbos processed simultaneously). For each decoder circuit, the latency is decreased, the area of the processing unit is inscreased by a factor m and the critical path and memory size are constant (the data rate is increased by m2 if we have m paralel decoders)