Thermo-mechanical analysis of flexible and stretchable systems

This paper presents a summary of the modeling and technology developed for flexible and stretchable electronics. The integration of ultra thin dies at package level, with thickness in the range of 20 to 30 μ m, into flexible and/or stretchable materials are demonstrated as well as the design and reliability test of stretchable metal interconnections at board level are analyzed by both experiments and finite element modeling. These technologies can achieve mechanically bendable and stretchable subsystems. The base substrate used for the fabrication of flexible circuits is a uniform polyimide layer, while silicones materials are preferred for the stretchable circuits. The method developed for chip embedding and interconnections is named Ultra Thin Chip Package (UTCP). Extensions of this technology can be achieved by stacking and embedding thin dies in polyimide, providing large benefits in electrical performance and still allowing some mechanical flexibility. These flexible circuits can be converted into stretchable circuits by replacing the relatively rigid polyimide by a soft and elastic silicone material. We have shown through finite element modeling and experimental validation that an appropriate thermo mechanical design is necessary to achieve mechanically reliable circuits and thermally optimized packages

Stress-Induced Delamination Of Through Silicon Via Structures

Continuous scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32 nm technology node in microelectronics. Recently three-dimensional (3-D) integration with through-silicon-vias (TSVs) has emerged as an effective solution to meet the future interconnect requirement. Thermo-mechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. This paper examines the effect of thermal stresses on interfacial reliability of TSV structures. First, the three-dimensional distribution of the thermal stress near the TSV and the wafer surface is analyzed. Using a linear superposition method, a semi-analytic solution is developed for a simplified structure consisting of a single TSV embedded in a silicon (Si) wafer. The solution is verified for relatively thick wafers by comparing to numerical results obtained by finite element analysis (FEA). Results from the stress analysis suggest interfacial delamination as a potential failure mechanism for the TSV structure. Analytical solutions for various TSV designs are then obtained for the steady-state energy release rate as an upper bound for the interfacial fracture driving force, while the effect of crack length is evaluated numerically by FEA. Based on these results, the effects of TSV designs and via material properties on the interfacial reliability are elucidated. Finally, potential failure mechanisms for TSV pop-up due to interfacial fracture are discussed.Aerospace Engineerin

Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law and system miniaturization with System-On-Package (SOP) paradigm has resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. The trend towards 3D silicon system integration is expected to downscale IC I/O pad pitches from 40µm to 1- 5 µm in future. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. As supply currents will increase upto 220 A by 2012, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer size technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Recently, many research groups have investigated various techniques for copper-copper direct bonding. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. In the present study, copper-copper bonding at ultra fine-pitch using advanced nano-conductive and non-conductive adhesives is evaluated. The proposed copper-copper based interconnects using advanced conductive and non-conductive adhesives will be a new fundamental and comprehensive paradigm to solve all the four barriers: 1) I/O pitch 2) Electrical performance 3) Reliability and 4) Cost. This thesis investigates the mechanical integrity and reliability of copper-copper bonding using advanced adhesives through test vehicle fabrication and reliability testing. Test vehicles were fabricated using low cost electro-deposition techniques and assembled onto glass carrier. Experimental results show that proposed copper-copper bonding using advanced adhesives could potentially meet all the system performance requirements for the emerging micro/nano-systems.M.S.Committee Chair: Prof. Rao R Tummala; Committee Member: Dr. Jack Moon; Committee Member: Dr. P M Ra

Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications

Im Rahmen der vorliegenden Dissertation zum Thema „Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications“ wurde auf Basis einer 130 nm SiGe BiCMOS Technologie ein Through-Silicon Via (TSV) Technologiemodul zur Herstellung elektrischer Durchkontaktierungen für die Anwendung im Millimeterwellen und Sub-THz Frequenzbereich entwickelt. TSVs wurden mittels elektromagnetischer Simulationen modelliert und in Bezug auf ihre elektrischen Eigenschaften bis in den sub-THz Bereich bis zu 300 GHz optimiert. Es wurden die Wechselwirkungen zwischen Modellierung, Fertigungstechnologie und den elektrischen Eigenschaften untersucht. Besonderes Augenmerk wurde auf die technologischen Einflussfaktoren gelegt. Daraus schlussfolgernd wurde das TSV Technologiemodul entwickelt und in eine SiGe BiCMOS Technologie integriert. Hierzu wurde eine Via-Middle Integration gewählt, welche eine Freilegung der TSVs von der Wafer Rückseite erfordert. Durch die geringe Waferdicke von ca. 75 μm wird einen Carrier Wafer Handling Prozess verwendet. Dieser Prozess wurde unter der Randbedingung entwickelt, dass eine nachfolgende Bearbeitung der Wafer innerhalb der BiCMOS Pilotlinie erfolgen kann. Die Rückseitenbearbeitung zielt darauf ab, einen Redistribution Layer auf der Rückseite der BiCMOS Wafer zu realisieren. Hierzu wurde ein Prozess entwickelt, um gleichzeitig verschiedene TSV Strukturen mit variablen Geometrien zu realisieren und damit eine hohe TSV Design Flexibilität zu gewährleisten. Die TSV Strukturen wurden von DC bis über 300 GHz charakterisiert und die elektrischen Eigenschaften extrahiert. Dabei wurde gezeigt, dass TSV Verbindungen mit sehr geringer Dämpfung <1 dB bis 300 GHz realisierbar sind und somit ausgezeichnete Hochfrequenzeigenschaften aufweisen. Zuletzt wurden vielfältige Anwendungen wie das Grounding von Hochfrequenzschaltkreisen, Interposer mit Waveguides und 300 GHz Antennen dargestellt. Das Potential für Millimeterwellen Packaging und 3D Integration wurde evaluiert. TSV Technologien sind heutzutage in vielen Anwendungen z.B. im Bereich der Systemintegration von Digitalschaltkreisen und der Spannungsversorgung von integrierten Schaltkreisen etabliert. Im Rahmen dieser Arbeit wurde der Einsatz von TSVs für Millimeterwellen und dem sub-THz Frequenzbereich untersucht und die Anwendung für den sub-THz Bereich bis 300 GHz demonstriert. Dadurch werden neue Möglichkeiten der Systemintegration und des Packaging von Höchstfrequenzsystemen geschaffen.:Bibliographische Beschreibung List of symbols and abbreviations Acknowledgement 1. Introduction 2. FEM Modeling of BiCMOS & Interposer Through-Silicon Vias 3. Fabrication of BiCMOS & Silicon Interposer with TSVs 4. Characterization of BiCMOS Embedded Through-Silicon Vias 5. Applications 6. Conclusion and Future Work 7. Appendix 8. Publications & Patents 9. Bibliography 10. List of Figures and Table

Heterogeneous 2.5D integration on through silicon interposer

© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity

Thermo-mechanical stress measurement and analysis in three dimensional interconnect structures

Three-dimensional (3-D) integration is effective to overcome the wiring limit imposed on device density and performance with continued scaling. The application of TSV (Through-Silicon Via) is essential for 3D IC integration. TSVs are embedded into the silicon substrate to form vertical, electrical connections between stacked IC chips. However, due to the large CTE mismatch between Silicon and Copper, thermal stresses are induced by various thermal histories from the device processing, and they have caused serious concerns regarding the thermal-mechanical reliability. Firstly, a semi-analytic approach is introduced to understand stress distributions in TSV structures. This is followed by application of finite element analysis for more accurate prediction of stress behavior according to the real geometry of the sample. The conventional Raman method is used to measure the linear combination of in-plane stress components near silicon top surface Secondly, the limitation of conventional Raman method is discussed: only certain linear combination of in-plane stress, instead of separate value for each stress components, can be obtained. Two different kinds of innovative Raman measurements have been developed and employed to study the normal stress components separately. Both of them take advantages of different laser polarization profiles to resolve the normal stress components separately based on experimental data. The top-down Raman measurements utilize so called “high NA effect” to obtain additional information, and can resolve all 3 normal stress components. Independent bending beam experiments are used to validate the results from cross-section Raman measurement on the same sample. The correlation between top-down Raman measurement and cross-section Raman measurement are investigated as well. Lastly, as a typical example of 3D IC package, a stack-die memory package is presented. Finite element analysis combined with cross-section Raman measurement and high resolution moiré interferometry were employed to investigate the thermal-mechanical reliability and chip-package interaction of the stack-die memory structure.Physic

All-copper chip-to-substrate interconnects for high performance integrated circuit devices

In this work, all-copper connections between silicon microchips and substrates are developed. The semiconductor industry advances the transistor density on a microchip based on the roadmap set by Moore's Law. Communicating with a microprocessor which has nearly one billion transistors is a daunting challenge. Interconnects from the chip to the system (i.e. memory, graphics, drives, power supply) are rapidly growing in number and becoming a serious concern. Specifically, the solder ball connections that are formed between the chip itself and the package are challenging to make and still have acceptable electrical and mechanical performance. These connections are being required to increase in number, increase in power current density, and increase in off-chip operating frequency. Many of the challenges with using solder connections are limiting these areas. In order to advance beyond the limitations of solder for electrical and mechanical performance, a novel approach to creating all-copper connections from the chip-to-substrate has been developed. The development included characterizing the electroless plating and annealing process used to create the connections, designing these connections to be compatible with the stress requirements for fragile low-k devices, and finally by improving the plating/annealing process to become process time competitive with solder. It was found that using a commercially available electroless copper bath for the plating, followed by annealing at 180 C for 1 hour, the shear strength of the copper-copper bond was approximately 165 MPa. This work resulted in many significant conclusions about the mechanism for bonding in the all-copper process and the significance of materials and geometry on the mechanical design for these connections.Ph.D.Committee Chair: Kohl, Paul; Committee Member: Bidstrup Allen, Sue Ann; Committee Member: Fuller, Thomas; Committee Member: Hesketh, Peter; Committee Member: Hess, Dennis; Committee Member: Meindl, Jame

Contributions à l’intégration des procédés de fabrication et d'encapsulation d’un commutateur MEMS RF ohmique

Abstract : This dissertation presents studies to resolve process integration problems in the fabrication of packaged radio frequency microelectromechanical system (RF MEMS) ohmic switches with a Au-Ru contact metallurgy and Al-Ge eutectic wafer bonding for wafer-level packaging (WLP). While unpackaged RF MEMS switches have shown promising attributes poor reliability has limited their development into practical products, demanding compatibility with a hermetic sealing solution. The first article, titled ‘Exploring Ru compatibility with Al-Ge eutectic wafer bonding,’ and its supplemental material examine bond impacts associated with the refractory metal ruthenium (Ru). The compatibility of Ru with a wafer bonding process has been virtually unexplored. The main text of this section outlines the results of blanket deposition annealing experiments with Ru, Al and Ge configurations to address concerns of ternary alloy poisoning, melt wettability on Ru, and Ru as a diffusing contaminant in Al and Ge. A brief exploration of the composition process window for Al-Ge alloys contaminated with Ru is made from available phase diagrams, and strong bond outcomes with real product wafers with Ru contacts are presented. The article concludes that Ru has high compatibility within an expected narrow composition process window of marginally reduced melting temperature for Al-Ge alloy. Supplemental material addresses additional process integration problems in the real bond process associated with Ru: alumina thickening, Ru contamination and Al hillock aggravation. These are challenges for the Al surface, which progressively loses bonding ability with Ge through the fabrication process, and can be obviated with unprocessed bonding Al without Ru exposure. The second article, titled ‘Mitigating re-entrant etch profile undercut in Au etch with an aqua regia variant,’ and its supplemental material examine processed Au outcomes and bond-on-contact consequences primarily inflicted on Au. Thermally-stable Au metallization to Si for microswitch contacts in packaged devices is a considerable integration challenge. The main text of this section outlines an etch profile investigation of Au metallization stack variants with adhesion layers to discriminate delamination-based undercutting from galvanic undercutting when using an aqua regia-based solution, showing which mechanism is applicable for this etchant. A brief examination of the electrochemistry of the etchant is made to explain the unusual outcome of mitigated galvanic undercut confirmed by this analysis, with delamination control eliminating or minimizing undercut for thick Au films. In the supplemental material Au surface evolution is tracked across the fabrication process, with the wafer bonding thermal cycle being deemed most significant. Au hillocking and delamination are the primary challenges, and segmentation of Au features is a leading mitigation option that increases the impact of any Au undercut. Together these chapters develop an improved understanding of contact/bond compatibility. Necessary and promising future work for RF MEMS microfabrication and packaging is outlined at the conclusion of this dissertation.Cette thèse présente des études visant à résoudre les problèmes d’intégration de procédés dans la fabrication de commutateurs radiofréquence ohmiques de systèmes microélectromécaniques de (RF MEMS) encapsulés par une métallurgie de contact Au-Ru et un collage eutectique de gaufres Al-Ge pour l'encapsulation au niveau des gaufres (Wafer-Level Packaging, WLP). Bien que les commutateurs MEMS RF non encapsules aient montré des attributs prometteurs, leur faible fiabilité a limité leur développement en produits pratiques, exigeant la compatibilité avec une solution de collage hermétique. Le premier article, intitulé ‹‹Exploring Ru compatibility with Al-Ge eutectic wafer bonding››, et son supplément examinent les effets de liaison associés au ruthénium (Ru), un métal réfractaire. La compatibilité du Ru avec un procédé de collage de gaufres a été très par inexplorée. Le texte principal de cette section présente les résultats d'expériences de recuit des dépôts pleine plaque avec des configurations de Ru, Al et Ge pour répondre aux préoccupations concernant l'empoisonnement des alliages ternaires, la mouillabilité de la masse fondue sur le Ru, et le Ru en tant que contaminant diffusant dans Al et Ge. Une brève exploration de la fenêtre de procédé de composition pour les alliages Al-Ge contaminés par Ru est faite à partir des diagrammes de phase disponibles, et des résultats de collage fort avec des gaufres de produits réels avec des contacts Ru sont présentés. L'article conclut que Ru a une compatibilité élevée dans une fenêtre de procédé de composition étroite attendue de température de fusion marginalement réduite pour l'alliage Al-Ge. Des documents complémentaires traitent de problèmes d'intégration autres dans le procédé de collage réel associés au Ru: épaississement de l'alumine, contamination par le Ru et aggravation de la topographie d'Al. Il s'agit de défis pour la surface de l'aluminium, qui perd progressivement sa capacité de collage avec le Ge au cours du procédé de fabrication, et qui peuvent être évités avec de l'aluminium de collage non traité sans exposition au Ru. Le deuxième article, intitulé ‹‹Mitigating re-entrant etch profile undercut in Au etch with an aqua regia variant››, et son matériel supplémentaire examinent les résultats de la gravure de l'Au et les conséquences de la liaison sur le contact principalement infligées à l'Au. La métallisation thermiquement stable de l'Au sur le Si pour les contacts dans les dispositifs encapsulés est un défi d'intégration considérable. Le texte principal de cette section décrit une étude sur le profil de gravure de variantes d'empilement de métallisation Au avec des couches d'adhérence pour distinguer la sous-coupe basée sur la délamination de la sous-coupe galvanique lors de l'utilisation d'une solution à base d'eau régale, montrant quel mécanisme est applicable pour ce réactif de gravure. Un bref examen de l'électrochimie de l'agent de gravure est effectué pour expliquer le résultat inhabituel de la surgravure galvanique atténuée confirmée par cette analyse, le contrôle de la délamination éliminant ou minimisant la surgravure pour les films d'Au épais. Dans les documents complémentaires, l'évolution de la surface de l'or est suivie tout au long du procédé de fabrication, le cycle thermique de collage des gaufres étant considéré comme le plus important. La formation de bosses et le délaminage de l'or sont les principaux défis à relever, et la segmentation des caractéristiques de l'or est une option d'atténuation importante qui augmente l'impact de toute contre-dépouille de l'or. Ensemble, ces chapitres permettent de mieux comprendre la compatibilité contact/liaison. Les travaux futurs nécessaires et prometteurs pour la microfabrication et le conditionnement des MEMS RF sont présentés en conclusion de cette thèse