Concepts and methods in optimization of integrated LC VCOs

Underlying physical mechanisms controlling the noise properties of oscillators are studied. This treatment shows the importance of inductance selection for oscillator noise optimization. A design strategy centered around an inductance selection scheme is executed using a practical graphical optimization method to optimize phase noise subject to design constraints such as power dissipation, tank amplitude, tuning range, startup condition, and diameters of spiral inductors. The optimization technique is demonstrated through a design example, leading to a 2.4-GHz fully integrated, LC voltage-controlled oscillator (VCO) implemented using 0.35-μm MOS transistors. The measured phase-noise values are -121, -117, and -115 dBc/Hz at 600-kHz offset from 1.91, 2.03, and 2.60-GHz carriers, respectively. The VCO dissipates 4 mA from a 2.5-V supply voltage. The inversion mode MOSCAP tuning is used to achieve 26% of tuning range. Two figures of merit for performance comparison of various oscillators are introduced and used to compare this work to previously reported results

High Performance Optical Transmitter Ffr Next Generation Supercomputing and Data Communication

High speed optical interconnects consuming low power at affordable prices are always a major area of research focus. For the backbone network infrastructure, the need for more bandwidth driven by streaming video and other data intensive applications such as cloud computing has been steadily pushing the link speed to the 40Gb/s and 100Gb/s domain. However, high power consumption, low link density and high cost seriously prevent traditional optical transceiver from being the next generation of optical link technology. For short reach communications, such as interconnects in supercomputers, the issues related to the existing electrical links become a major bottleneck for the next generation of High Performance Computing (HPC). Both applications are seeking for an innovative solution of optical links to tackle those current issues. In order to target the next generation of supercomputers and data communication, we propose to develop a high performance optical transmitter by utilizing CISCO Systems®\u27s proprietary CMOS photonic technology. The research seeks to achieve the following outcomes: 1. Reduction of power consumption due to optical interconnects to less than 5pJ/bit without the need for Ring Resonators or DWDM and less than 300fJ/bit for short distance data bus applications. 2. Enable the increase in performance (computing speed) from Peta-Flop to Exa-Flops without the proportional increase in cost or power consumption that would be prohibitive to next generation system architectures by means of increasing the maximum data transmission rate over a single fiber. 3. Explore advanced modulation schemes such as PAM-16 (Pulse-Amplitude-Modulation with 16 levels) to increase the spectrum efficiency while keeping the same or less power figure. This research will focus on the improvement of both the electrical IC and optical IC for the optical transmitter. An accurate circuit model of the optical device is created to speed up the performance optimization and enable co-simulation of electrical driver. Circuit architectures are chosen to minimize the power consumption without sacrificing the speed and noise immunity. As a result, a silicon photonic based optical transmitter employing 1V supply, featuring 20Gb/s data rate is fabricated. The system consists of an electrical driver in 40nm CMOS and an optical MZI modulator with an RF length of less than 0.5mm in 0.13&mu m SOI CMOS. Two modulation schemes are successfully demonstrated: On-Off Keying (OOK) and Pulse-Amplitude-Modulation-N (PAM-N N=4, 16). Both versions demonstrate signal integrity, interface density, and scalability that fit into the next generation data communication and exa-scale computing. Modulation power at 20Gb/s data rate for OOK and PAM-16 of 4pJ/bit and 0.25pJ/bit are achieved for the first time of an MZI type optical modulator, respectively

Design Of A 2.4 Ghz Low Power Lc Vco In Umc 0.18u Technology

Tez (Yüksek Lisans) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2007Thesis (M.Sc.) -- İstanbul Technical University, Institute of Science and Technology, 2007Bu çalışmada, Bluetooth uygulamalarında kullanılmak üzere 2.45GHz merkez frekansında çalışan, frekans ayarlaması 2.2GHz ile 2.7GHz arasında değişen, düşük güç (2mW) tüketimi sağlayan bir LC GKO (VCO) tasarlanmıştır. Faz gürültüsünü minimize etmek maksadıyla 4 bit anahtarlamalı IMOS dizisinden yararlanılmıştır. Ayrıca frekansın ince ayarı için kapasite kuplajlı diyot varaktör devresi eklenmiştir. Bu frekans ayarlama tekniğinin faz gürültüsüne etkisi en kötü hal için 50kHz ofsette yaklaşık olarak 2dBc/Hz olup yüksek ofsetlerde yok denecek kadar azdır. Devrenin kaba kontrol gerilimleri 1.4V ve 0V olup, ince ayar gerilimi ise 0.5V ile 1.4V arasındadır. Besleme geriliminin 1.4V olduğu dikkate alındığında devre yüksek entegrasyon olanağı sunmaktadır. Faz gürültüsü 50kHz ofsette -88.6dBc/Hz ile -94.36dBc/Hz arasında olup 3MHz ofsette ise -128.3dBc/Hz ile -130.5dBc/Hz değerlerine ulaşmaktadır.Bu devreye ek olarak daha düşük gerilimli farklı topolojiler aynı akım akıtacak şekilde tasarlanmış ve tezin aynı zamanda ISM bandında çalışan düşük güç sarfiyatı isteyen uygulamalarda gerekli olacak bir GKO ihtiyacı için karşılaştırmalı bir çalışma olması sağlanmıştır.In this study, a low power LC VCO which operates at a center frequency of 2.45GHz over the range between 2.2GHz and 2.7GHz is designed for Bluetooth applications. The oscillator consumes 2mW at a supply voltage of 1.4V. To minimize the phase noise generated by the varactor through AM-PM conversion, 4bits SCA varactor is implemented by employing IMOS varactors. For fine tuning of frequency, a capacitor coupled diode varactor structure is designed. The effect of this overall varactor structure on the phase noise is around 2dBc/Hz at 50kHz offset for the worst case whereas it is negligble at high offsets. The coarse control tuning voltage values are 0V and 1.4V and the fine tuning control voltage varies from 0.5V to 1.4V. Hence, a high integration is achieved by keeping the external voltage at power supply voltage. The phase noise is between -88.6dBc/Hz and -94.36dBc/Hz at 50kHz offset, and between -128.3dBc/Hz and -130.5dBc/Hz at 3MHz offset. In addition to this, several circuits enabling lower supply voltage are simulated by keeping the same current in order to constitute a comparative study for low power applications which do not require stringent phase noise specification at 2.4GHz.Yüksek LisansM.Sc

A dual-mode Q-enhanced RF front-end filter for 5 GHz WLAN and UWB with NB interference rejection

The 5 GHz Wireless LAN (802.11a) is a popular standard for wireless indoor communications providing moderate range and speed. Combined with the emerging ultra Wideband standard (UWB) for short range and high speed communications, the two standards promise to fulfil all areas of wireless application needs. However, due to the overlapping of the two spectrums, the stronger 802.11a signals tend to interfere causing degradation to the UWB receiver. This presents one of the main technical challenges preventing the wide acceptance of UWB. The research work presented in this thesis is to propose a low cost RF receiver front-end filter topology that would resolve the narrowband (NB) interference to UWB receiver while being operable in both 802.11a mode and UWB mode. The goal of the dual mode filter design is to reduce cost and complexity by developing a fully integrated front-end filter. The filter design utilizes high Q passive devices and Q-enhancement technique to provide front-end channel-selection in NB mode and NB interference rejection in UWB mode. In the 802.11a NB mode, the filter has a tunable gain of 4 dB to 25 dB, NF of 8 dB and an IIP3 between -47 dBm and -18 dBm. The input impedance is matched at -16 dB. The frequency of operation can be tuned from 5.15 GHz to 5.35 GHz. In the UWB mode, the filter has a gain of 0 dB to 8 dB across 3.1 GHz to 9 GHz. The filter can reject the NB interference between 5.15 GHz to 5.35 GHz at up to 60 dB. The Q of the filter is tunable up to a 250 while consuming a maximum of 23.4 mW of power. The fully integrated dual mode filter occupies a die area of 1.1 mm2

High-speed communication circuits: voltage control oscillators and VCO-derived filters

Voltage Controlled Oscillators (VCO) and filters are the two main topics of focus in this dissertation.;A temperature and process compensated VCO, which is designed to operate at 2 GHz, and whose frequency variation due to incoming data is limited to 1% of its center frequency was presented. The test results show that, without process changes present, the frequency variation due to a temperature change over 0°C to 100°C is around 1.1% of its center frequency. This is a reduction of a factor of 10 when compared to the temperature variation of a conventional VCO.;A new method of designing continuous-time monolithic filters derived from well-known voltage controlled oscillators (VCOs) was introduced. These VCO-derived filters are capable of operating at very high frequencies in standard CMOS processes. Prototype low-pass and band-pass filters designed in a TSMC 0.25 mum process are discussed. Simulation results for the low-pass filter designed for a cutoff frequency of 4.3 GHz show a THD of -40 dB for a 200 mV peak-peak sinusoidal input. The band-pass filter has a resonant frequency programmable from 2.3 GHz to 3.1 GHz, a programmable Q from 3 to 85, and mid-band THD of -40 dB for an 80 mV peak-peak sinusoidal input signal.;A third contribution in this dissertation was the design of a new current mirror with accurate mirror gain for low beta bipolar transistors. High mirror gain accuracy is achieved by using a split-collector transistor to compensate for base currents of the source-coupled

Design of low power 2.4GHz CMOS LC balanced oscillators with low phase noise and large tuning range

The design of two 2.4GHz CMOS LC balanced oscillators in the 0.25μm National BiCMOS process for Bluetooth specifications is presented. These oscillators achieve low phase noise with low power consumption. At a frequency offset of 500KHz from the 2.11GHz carrier, the measured phase noise is -101.9dBc/Hz for the NMOS oscillator with a power dissipation of 12.5mW. The complementary oscillator has a phase noise of -103.6dBc/Hz at 500KHz offset from the 2.19GHz carrier and a power dissipation of 6.25mW from a 2.5V power supply. A wide tuning range of 16% is obtained by means of a PMOS varactor in conjunction with an array of switched capacitors

Design and modeling of a CMOS VCO using wave digital filters / by WeiBo Li.

Wave digital filters (WDFs) transform an analog network into a topologically equivalent digital structure. A natural application of WDF is the simulation of electric circuits since measurements of any desired node voltages and branch currents are available during all time-steps in WDF structures. WDF structures tend to preserve most of the good properties of their analog counterpart. In this work, WDF techniques applied to transient simulation are studied. After a review o f the basic theory of WDFs and the treatment of nonlinear elements in WDFs, WDF simulations for different circuits, including a simple RC circuit, an anharmonic oscillator and a CMOS LC voltage controlled oscillator (VCO), are presented. Special detail is put on the design and modeling of the LC VCO. The LC VCO was designed and fabricated using the TSMC (Taiwan Semiconductor Manufacturing Co., LTD) CMOS 0.1 Sum technology. The linear frequency tuning range of the LC VCO is from 2.526 GHz to 3.015 GHz for control voltages from 0 to 1 V with a 1.712 mA tail current. WDF simulation results are compared with the exact solution if possible or otherwise with the results obtained with other simulation methods. The comparison shows that WDF techniques are efficient for the simulations of linear circuits and circuits with one nonlinear element. The potential of WDF for the simulation of large networks with many nonlinear elements is also discussed in this thesis

Giga-hertz CMOS voltage controlled oscillators.

Leung Lai-Kan.Thesis (M.Phil.)--Chinese University of Hong Kong, 2001.Includes bibliographical references (leaves 131-154).Abstracts in English and Chinese.Abstract --- p.iAcknowledgement --- p.iiiTable of Contents --- p.ivList of Figures --- p.ixList of Tables --- p.xvChapter Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Overview --- p.1Chapter 1.2 --- Objectives --- p.2Chapter 1.3 --- Thesis Organization --- p.4Chapter Chapter 2 --- Fundamentals of Voltage Controlled Oscillators --- p.6Chapter 2.1 --- Definition of Commonly Used Figures of Merit --- p.6Chapter 2.1.1 --- Cutoff frequency --- p.6Chapter 2.1.2 --- Center Frequency --- p.8Chapter 2.1.3 --- Tuning Range --- p.8Chapter 2.1.4 --- Tuning Sensitivity --- p.8Chapter 2.1.5 --- Output Power --- p.8Chapter 2.1.6 --- Power Consumption --- p.9Chapter 2.1.7 --- Supply Pulling --- p.9Chapter 2.2 --- Phase Noise --- p.9Chapter 2.2.1 --- Definition of Phase Noise --- p.9Chapter 2.2.2 --- Phase Noise Specification --- p.11Chapter 2.2.3 --- Leeson's formula --- p.12Chapter 2.2.4 --- Models developed by J. Cranincks and M. Steyaert10 --- p.13Chapter 2.2.5 --- Linear Time-Variant Phase Noise Model --- p.13Chapter 2.3 --- Building Blocks of Voltage Controlled Oscillators --- p.17Chapter 2.3.1 --- FETs --- p.17Chapter 2.3.2 --- Varactor --- p.18Chapter 2.3.3 --- Spiral Inductor --- p.21Chapter 2.3.4 --- Modeling of the Spiral Inductor --- p.24Chapter 2.3.5 --- Analysis and Simulation --- p.26Chapter Chapter 3 --- Digital Controlled Oscillator --- p.28Chapter 3.1 --- Introduction --- p.28Chapter 3.2 --- General Principle of Oscillation --- p.28Chapter 3.3 --- Different Oscillator Architectures --- p.30Chapter 3.3.1 --- Single-ended Ring Oscillator --- p.30Chapter 3.3.2 --- Differential Ring Oscillator --- p.32Chapter 3.3.3 --- CMOS Injection-locked Oscillator --- p.33Chapter 3.4 --- Basic Principle of the Injection-locked Oscillator --- p.34Chapter 3.5 --- Digital Controlled Oscillator --- p.36Chapter 3.5.1 --- R-2R Digital-to-Analog Converter --- p.37Chapter 3.6 --- Injection Locking --- p.42Chapter 3.6.1 --- Synchronization Model of the Injection Locked Oscillator --- p.42Chapter 3.7 --- Simulation Results --- p.44Chapter 3.7.1 --- Frequency Tuning Characteristics --- p.44Chapter 3.7.2 --- Phase Noise Performance --- p.47Chapter 3.7.3 --- Locking Characteristics --- p.48Chapter 3.7.4 --- Sensitivity to Supply Voltage and Temperature --- p.48Chapter 3.8 --- Conclusion --- p.49Chapter Chapter 4 --- CMOS LC Voltage Controlled Oscillator --- p.51Chapter 4.1 --- Introduction --- p.51Chapter 4.2 --- LC Oscillator --- p.52Chapter 4.3 --- Circuit Design --- p.54Chapter 4.3.1 --- Oscillation Frequency --- p.55Chapter 4.3.2 --- Oscillation Amplitude --- p.58Chapter 4.3.3 --- Transistor Sizing --- p.59Chapter 4.3.4 --- Power Consumption --- p.62Chapter 4.3.5 --- Tuning Range --- p.62Chapter 4.3.6 --- Phase Noise Analysis --- p.63Chapter 4.4 --- Conclusion --- p.70Chapter Chapter 5 --- LC Quadrature Voltage Controlled Oscillator --- p.71Chapter 5.1 --- Introduction --- p.71Chapter 5.2 --- Conventional CMOS Quadrature LC Voltage Controlled Oscillator --- p.73Chapter 5.3 --- Operational Principle of the CMOS Quadrature LC Voltage Controlled Oscillator --- p.74Chapter 5.3.1 --- General Explanation --- p.74Chapter 5.3.2 --- Mathematical Analysis --- p.75Chapter 5.3.3 --- Drawback of the Conventional CMOS LC Quadrature VCO --- p.77Chapter 5.4 --- Novel CMOS Low Noise Quadrature Voltage Controlled Oscillator --- p.78Chapter 5.4.1 --- Equivalent Output Noise due to the Coupling Transistor --- p.80Chapter 5.4.2 --- Linear Time Varying Model for the Analysis of Total Phase Noise --- p.83Chapter 5.4.3 --- Tuning Range --- p.94Chapter 5.4.4 --- Start-up Condition --- p.95Chapter 5.4.5 --- Power Consumption --- p.97Chapter 5.5 --- New Tuning Mechanism of the Proposed LC Quadrature VCO --- p.98Chapter 5.6 --- Modified Version of the Proposed LC Quadrature Voltage Controlled Oscillator --- p.105Chapter 5.7 --- Conclusion --- p.108Chapter Chapter 6 --- Layout Consideration --- p.109Chapter 6.1 --- Substrate Contacts --- p.109Chapter 6.2 --- Guard Rings --- p.110Chapter 6.3 --- Thermal Noise of the Gate Interconnect --- p.111Chapter 6.4 --- Use of Different Layers of Metal for Interconnection --- p.112Chapter 6.5 --- Slicing of Transistors --- p.113Chapter 6.6 --- Width of Interconnecting Wires and Numbers of Vias --- p.114Chapter 6.7 --- Matching of Devices --- p.114Chapter 6.8 --- Die Micrographs of the Prototypes of the Oscillators --- p.115Chapter Chapter 7 --- Experimental Results --- p.118Chapter 7.1 --- Methodology --- p.118Chapter 7.2 --- Evaluation Board --- p.119Chapter 7.3 --- Measurement Setup --- p.123Chapter 7.4 --- Experimental Results --- p.125Chapter 7.4.1 --- CMOS Injection Locked Oscillator --- p.125Chapter 7.4.2 --- LC Differential Voltage Controlled Oscillator --- p.128Chapter 7.4.3 --- LC Quadrature Voltage Controlled Oscillator --- p.132Chapter 7.5 --- Summary of Performance --- p.139Chapter Chapter 8 --- Conclusion --- p.142Chapter 8.1 --- Contribution --- p.142Chapter 8.2 --- Further Development --- p.143Chapter Chapter 9 --- Appendix --- p.145Chapter 9.1 --- Circuit Transformation --- p.145Chapter 9.2 --- Derivation of the Inductor Model with PGS --- p.146Chapter 9.2.1 --- "Inductance," --- p.146Chapter 9.2.2 --- "Series Resistance, Rs" --- p.146Chapter 9.2.3 --- Series Capacitance --- p.147Chapter 9.2.4 --- Shunt Oxide Capacitance --- p.147Chapter 9.3 --- Calculation of Phase Noise Using the Linear Time Variant Model --- p.148Chapter Chapter 10 --- Bibliography --- p.15

A Low Jitter Wideband Fractional-N Subsampling Phase Locked Loop (SSPLL)

Frequency synthesizers have become a crucial building block in the evolution of modern communication systems and consumer electronics. The spectral purity performance of frequency synthesizers limits the achievable data-rate and presents a noise-power tradeoff. For communication standards such as LTE where the channel spacing is a few kHz, the synthesizers must provide high frequencies with sufficiently wide frequency tuning range and fine frequency resolutions. Such stringent performance must be met with a limited power and small chip area. In this thesis a wideband fractional-N frequency synthesizer based on a subsampling phase locked loop (SSPLL) is presented. The proposed synthesizer which has a frequency resolution less than 100Hz employs a digital fractional controller (DFC) and a 10-bit digital-to-time converter (DTC) to delay the rising edges of the reference clock to achieve fractional phase lock. For fast convergence of the delay calibration, a novel two-step delay correlation loop (DCL) is employed. Furthermore, to provide optimum settling and jitter performance, the loop transfer characteristics during frequency acquisition and phase-lock are decoupled using a dual input loop filter (DILF). The fractional-N sub-sampling PLL (FNSSPLL) is implemented in a TSMC 40nm CMOS technology and occupies a total active area of 0.41mm^2. The PLL operates over frequency range of 2.8 GHz to 4.3 GHz (42% tuning range) while consuming 9.18mW from a 1.1V supply. The integrated jitter performance is better than 390 fs across all fractional frequency channel. The worst case fractional spur of -48.3 dBc occurs at a 650 kHz offset for a 3.75GHz fractional channel. The in-band phase noise measured at a 200 kHz offset is -112.5 dBc/Hz

Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers

In the field of radio receivers, down-conversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the receiver’s performance in terms of noise and linearity. On the other hand, most ADCs require some sort of reference signal in order to properly digitize an analog input signal. The implementation of this reference signal usually relies on bandgap circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this conventional approach, the work developed in this thesis aims to explore the viability behind the usage of a variable reference signal. Moreover, it demonstrates that not only can an input signal be properly digitized, but also shifted up and down in frequency, effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver chains can perform double-duty as both a quantizer and a mixing stage. The lesser known charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs, is used for a practical implementation, due to its feature of “pre-charging” the reference signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in a 0.13 μm CMOS technology validate the proposed technique