Field Programmable Gate Arrays Usage in Industrial Automation Systems

Tato disertační práce se zabývá využitím programovatelných hradlových polí (FPGA) v diagnostice měničů, využívajících spínaných IGBT tranzistorů. Je zaměřena na budiče těchto výkonových tranzistorů a jejich struktury. Přechodné jevy veličin, jako jsou IG, VGE, VCE během procesu přepínání (zapnutí, vypnutí), mohou poukazovat na degradaci IGBT. Pro měření a monitorování těchto veličin byla navržena nová architektura budiče IGBT. Rychlé měření a monitorování během přepínacího děje vyžaduje vysokou vzorkovací frekvenci. Proto jsou navrhovány paralelní vysokorychlostní AD převodníky (> 50 MSPS). Práce je zaměřena převážně na návrh zařízení s FPGA včetně hardware a software. Byla navržena nová deska plošných spojů s FPGA, která plní požadované funkce, jako je řízení IGBT pomocí vícenásobných paralelních koncových stupňů, monitorování a diagnostiku, a propojení s řídicí jednotkou měniče.This doctoral thesis deals with the usage of Field Programmable Gate Arrays (FPGAs) in a diagnosis of power inverters which use the IGBTs transistors as switching devices. It is focused on the IGBT gate drives and their structures. As long as the transient phenomena and other quantities such as IG, VGE, VCE shows the IGBT degradation during the switching process (turn-on, turn-off), a new IGBT gate driver architecture is proposed for measuring and monitoring these quantities. Quick measurements and monitoring during the IGBT switching process require high sampling frequencies. Therefore, high speed parallel ADC converters (> 50MSPS) are proposed. The thesis is focused on the FPGA design (hardware, software). A new FPGA board is designed for desired functions implementation such as IGBT driving using multiple stages, IGBT monitoring and diagnosis, and interfacing to inverter controller.

A field programmable gate array based modular motion control platform

The expectations from motion control systems have been rising day by day. As the systems become more complex, conventional motion control systems can not achieve to meet all the specifications with optimized results. This creates the necessity of fundamental changes in the infrastructure of the system. Field programmable gate array (FPGA) technology enables the reconfiguration of the digital hardware, thus dissolving the necessity of infrastructural changes for minor manipulations in the hardware even if the system is deployed. An FPGA based hardware system shrinks the size of the hardware hence the cost. FPGAs also provide better power ratings for the systems as well as a more reliable system with improved performance. As a trade off, the development is rather more difficult than software based systems, which also affects the research and development time of the overall system. In this paper a level of abstraction is introduced in order to diminish the requirement of advanced hardware description language (HDL) knowledge for implementing motion control systems thoroughly on an FPGA. The intellectual property library consists of synthesizable hardware modules specifically implemented for motion control purposes. Other parts of a motion control system, like user interface and trajectory generation, are implemented as software functions in order to protect the modularity of the system. There are also several external hardware designs for interfacing and driving various types of actuators

Implementation and verification of a hardware-basedcontroller for a three-phase induction motor on an FPGA

L’objectiu d’aquesta tesi és estudiar diverses tècniques de control motor per tal d’implementar i verificar un controlador basat en hardware per a un motor d’inducció trifàsic desenvolupat en llenguatge VHDL i funcionant en una FPGA Artix-7 (Xil-inx). Aquest controlador està basat en tècniques de variació de freqüència. Els mòduls que defineixen la descripció de hardware funcionen simultàniament entre ells, i permeten agilitzar el sistema, millorant el rendiment i la resposta del motor, en comparació amb un microcontrolador. Aquesta tesi està relacionada amb els sistemes digitals, l’electrònica de potència i els sistemes de control.Outgoin

Routing Physarum with electrical flow/current

Plasmodium stage of Physarum polycephalum behaves as a distributed dynamical pattern formation mechanism who's foraging and migration is influenced by local stimuli from a wide range of attractants and repellents. Complex protoplasmic tube network structures are formed as a result, which serve as efficient `circuits' by which nutrients are distributed to all parts of the organism. We investigate whether this `bottom-up' circuit routing method may be harnessed in a controllable manner as a possible alternative to conventional template-based circuit design. We interfaced the plasmodium of Physarum polycephalum to the planar surface of the spatially represented computing device, (Mills' Extended Analog Computer, or EAC), implemented as a sheet of analog computing material whose behaviour is input and read by a regular 5x5 array of electrodes. We presented a pattern of current distribution to the array and found that we were able to select the directional migration of the plasmodium growth front by exploiting plasmodium electro-taxis towards current sinks. We utilised this directional guidance phenomenon to route the plasmodium across its habitat and were able to guide the migration around obstacles represented by repellent current sources. We replicated these findings in a collective particle model of Physarum polycephalum which suggests further methods to orient, route, confine and release the plasmodium using spatial patterns of current sources and sinks. These findings demonstrate proof of concept in the low-level dynamical routing for biologically implemented circuit design

A Survey: Space Vector PWM (SVPWM) in 3φ Voltage Source Inverter (VSI)

Since last decades, the pulse width modulation (PWM) techniques have been an intensive research subject. Also, different kinds of methodologies have been presented on inverter switching losses, inverter output current/ voltage total harmonic distortion (THD), inverter maximum output of DC bus voltage. The Sinusoidal PWM is generally used to control the inverter output voltage and it helps to maintains drive performance. The recent years have seen digital modulation mechanisms based on theory of space vector i.e. Space vector PWM (SVPWM). The SVPWM mechanism offers the enhanced amplitude modulation indexes (MI) than sinusoidal PWM along with the reduction in the harmonics of inverter output voltage and reduced communication losses. Currently, the digital control mechanisms have got more attention than the analog counterparts, as the performance and reliability of microprocessors has increased. Most of the SVPWM mechanisms are performed by using the analog or digital circuits like microcontrollers and DSPs. From the recent study, analysis gives that use of Field Programmable Gate Arrays (FPGA) can offer more efficient and faster solutions. This paper discusses the numerous existing research aspects of FPGA realization for voltage source inverter (VSI) along with the future line of research

FPGA design methodology for industrial control systems—a review

This paper reviews the state of the art of fieldprogrammable gate array (FPGA) design methodologies with a focus on industrial control system applications. This paper starts with an overview of FPGA technology development, followed by a presentation of design methodologies, development tools and relevant CAD environments, including the use of portable hardware description languages and system level programming/design tools. They enable a holistic functional approach with the major advantage of setting up a unique modeling and evaluation environment for complete industrial electronics systems. Three main design rules are then presented. These are algorithm refinement, modularity, and systematic search for the best compromise between the control performance and the architectural constraints. An overview of contributions and limits of FPGAs is also given, followed by a short survey of FPGA-based intelligent controllers for modern industrial systems. Finally, two complete and timely case studies are presented to illustrate the benefits of an FPGA implementation when using the proposed system modeling and design methodology. These consist of the direct torque control for induction motor drives and the control of a diesel-driven synchronous stand-alone generator with the help of fuzzy logic

STEROWANIE PRĘDKOŚCIĄ WENTYLATORA PRZY UŻYCIU BEZPOŚREDNIO PROGRAMOWALNEJ MACIERZY BRAMEK (FPGA)

This article describes the implementation of a DC fan controller using a field-programmable gate array (FPGA). Hardware description language (VHDL) is used to design and implement the processor of this controller. The processor is composed of a memory block that has a function of generation a Look up Table (LUT). Data saved in the memory block are used to generate a triangular signal. A carried signal can be added. This signal can be generated from digital temperature sensors. A comparator compares between the triangular signal and the carried signal to generate a Pulse-Width Modulation (PWM) output that controls the fan speed. The fan speed depends on the digital temperature sensor output. When the output signal of the sensor equals the output of the triangular wave, the fan speed is maximal and the temperature is high. This design requires a FPGA board and software ISE 14.4.Artykuł przedstawia implementację sterownika DC wentylatora używając bezpośrednio programowalnej macierzy bramek - FPGA (ang. Field programmable gate array). Język VHDL (ang. Very High Speed Integrated Circuits Hardware Description Language ) użyto do projektowania i implementacji procesora tego kontrolera. Procesor składa się z bloku pamięci, mającej funkcję generowania struktury nazywanej tablicą (ang. Look up Table – LUT). Dane zapamiętane w bloku pamięci używane są do generowania przebiegów trójkątnych. Komparator porównuje sygnał użyteczny, ten wygenerowany przez cyfrowy czujnik temperatury, z sygnałem trójkątnym, aby sygnał wyjściowy modulowany szerokością impulsu (ang. PWM) regulował prędkość wentylatora. Prędkość wentylatora zależy od sygnału wyjściowego z cyfrowego czujnika temperatury. Kiedy sygnał wyjściowy czujnika jest równy fali trójkątnej, wtedy prędkość wentylatora jest maksymalna a temperatura jest wysoka. Takie projektowanie wymaga FPGA i software ISE 14.4

FPGA-based implementation of the back-EMF symmetric-threshold-tracking sensorless commutation method for brushless DC-machines

The operation of brushless DC permanent-magnet machines requires information of the rotor position to steer the semiconductor switches of the power-supply module which is commonly referred to as Brushless Commutation. Different sensorless techniques have been proposed to estimate the rotor position using current and voltage measurements of the machine. Detection of the back-electromotive force (EMF) zero-crossing moments is one of the methods most used to achieve sensorless control by predicting the commutation moments. Most of the techniques based on this phenomenon have the inherit disadvantage of an indirect detection of commutation moments. This is the result of the commutation moment occurring 30 electrical degrees after the zero-crossing of the induced back-emf in the unexcited phase. Often, the time difference between the zero crossing of the back-emf and the optimal current commutation is assumed constant. This assumption can be valid for steady-state operation, however a varying time difference should be taken into account during transient operation of the BLDC machine. This uncertainty degrades the performance of the drive during transients. To overcome this problem which improves the performance while keeping the simplicity of the back-emf zero-crossing detection method an enhancement is proposed. The proposed sensorless method operates parameterless in a way it uses none of the brushless dc-machine parameters. In this paper different aspects of experimental implementation of the new method as well as various aspects of the FPGA programming are discussed. Proposed control method is implemented within a Xilinx Spartan 3E XC3S500E board