Design and Assembly of High-Temperature Signal Conditioning System on LTCC with Silicon Carbide CMOS Circuits

The objective of the work described in this dissertation paper is to develop a prototype electronic module on a low-temperature co-fired ceramic (LTCC) material. The electronic module would perform signal conditioning of sensor signals (thermocouples) operating under extreme conditions for applications like gas turbines to collect data on the health of the turbine blades during operation so that the turbines do not require shutdown for inspection to determine if maintenance is required. The collected data can indicate when such shutdowns, which cost $1M per day, should be scheduled and maintenance actually performed. The circuits for the signal conditioning system within the prototype module must survive the extreme temperature, pressure, and centrifugal force, or G-force, present in these settings. Multiple fabrication runs on different integrated silicon carbide (SiC) process technologies have been carried out to meet the system requirements. The key circuits described in this dissertation are - two-stage op amp topologies and voltage reference, which are designed and fabricated in a new SiC CMOS process. The SiC two-stage op amp with PFET differential input pair showed 48.9 dB of DC gain at 500oC. The voltage reference is the first in SiC CMOS technology to employ an op amp-based topology. The op amp circuit in the voltage reference is a two-stage with NFET differential input pair that uses the indirect compensation technique for the first time in the SiC CMOS process to provide 42.5 dB gain at 350oC. The designed prototype module implemented with these circuits was verified to provide signal conditioning and signal transmission at 300oC. The signal transmission circuit on the module was also verified to operate with a resonant inductive wireless power transfer method at a frequency of 11.8 MHz for the first time. A second prototype module was also developed with the previously fabricated 1.2 µm SiC CMOS process. The second module was successfully tested (with wired power supply) to operate at 440oC inside a probe-station and also verified for the first time to sustain signal transmission (34.65 MHz) capability inside a spin-rig at a rotational speed of 10,920 rpm. All designed modules have dimensions of (length) 68.5 mm by (width) 34.3 mm to conform to the physical size requirements of the gas turbine blade

Next generation RFID telemetry design for biomedical implants.

The design and development of a Radio Frequency Identification (RFID) based pressure-sensing system to increase the range of current Intra-Ocular Pressure (IOP) sensing systems is described in this dissertation. A large number of current systems use near-field inductive coupling for the transfer of energy and data, which limits the operational range to only a few centimeters and does not allow for continuous monitoring of pressure. Increasing the powering range of the telemetry system will offer the possibility of continuous monitoring since the reader can be attached to a waist belt or put on a night stand when sleeping. The system developed as part of this research operates at Ultra-High Frequencies (UHF) and makes use of the electromagnetic far field to transfer energy and data, which increases the potential range of operation and allows for the use of smaller antennas. The system uses a novel electrically small antenna (ESA) to receive the incident RF signal. A four stage Schottky circuit rectifies and multiplies the received RF signal and provides DC power to a Colpitts oscillator. The oscillator is connected to a pressure sensor and provides an output signal frequency that is proportional to the change in pressure. The system was fabricated using a mature, inexpensive process. The performance of the system compares well with current state of the art, but uses a smaller antenna and a less expensive fabrication process. The system was able to operate over the desired range of 1 m using a half-wave dipole antenna. It was possible to power the system over a range of at least 6.4 cm when the electrically small antenna was used as the receiving antenna

Schottky Field Effect Transistors and Schottky CMOS Circuitry

It was the primary goal (and result) of the presented work to empirically demonstrate CMOS operation (i.e., inverter transfer characteristics) using metallic/Schottky source/drain MOSFETs (SFETs - Schottky Field Effect Transistors) fabricated on silicon-on-insulator (SOI) substrates - a first-ever in the history of SFET research. Due to its candidacy for present and future CMOS technology, many different research groups have explored different SFET architectures in an effort to maximize performance. In the presented work, an architecture known as a bulk switching SFET was fabricated using an implant-to-silicide (ITS) technique, which facilitates a high degree of Schottky barrier lowering and therefore an increase in current injection with minimal process complexity. The different switching mechanism realized with this technique also reduces the ambipolar leakage current that has so often plagued SFETs of more conventional design. In addition, these devices have been utilized in a patent pending approach that may facilitate an increase in circuit density for devices of a given size. In other words, for example, it may be possible to achieve circuit density equivalent to 65 nm technology using a 90 nm process, while at the same time preserving or reducing local interconnect density for enhanced overall system speed. Fabrication details and electrical results will be discussed, as well as some initial modeling efforts toward gaining insight into the details of current injection at the metal-semiconductor (M-S) interface. The challenges faced using the ITS approach at aggressive scales will be discussed, as will the potential advantages and disadvantages of other approaches to SFET technology

MOSFET zero-temperature-coefficient (ZTC) effect modeling anda analysis for low thermal sensitivity analog applications

Continuing scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technologies brings more integration and consequently temperature variation has become more aggressive into a single die. Besides, depending on the application, room ambient temperature may also vary. Therefore, procedures to decrease thermal dependencies of eletronic circuit performances become an important issue to include in both digital and analog Integrated Circuits (IC) design flow. The main purpose of this thesis is to present a design methodology for a typical CMOS Analog design flow to make circuits as insensitivity as possible to temperature variation. MOSFET Zero Temperature Coefficient (ZTC) and Transconductance Zero Temperature Coefficient (GZTC) bias points are modeled to support it. These are used as reference to deliver a set of equations that explains to analog designers how temperature will change transistor operation and hence the analog circuit behavior. The special bias conditions are analyzed using a MOSFET model that is continuous from weak to strong inversion, and both are proven to occur always from moderate to strong inversion operation in any CMOS fabrication process. Some circuits are designed using proposed methodology: two new ZTC-based current references, two new ZTC-based voltage references and four classical Gm-C circuits biased at GZTC bias point (or defined here as GZTC-C filters). The first current reference is a Self-biased CMOS Current Reference (ZSBCR), which generates a current reference of 5 A. It is designed in an 180 nm process, operating with a supply voltage from 1.4V to 1.8 V and occupying around 0:010mm2 of silicon area. From circuit simulations the reference shows an effective temperature coefficient (TCeff ) of 15 ppm/oC from 45 to +85oC, and a fabrication process sensitivity of = = 4:5%, including average process and local mismatch. Simulated power supply sensitivity is estimated around 1%/V. The second proposed current reference is a Resistorless Self-Biased ZTC Switched Capacitor Current Reference (ZSCCR). It is also designed in an 180 nm process, resulting a reference current of 5.88 A under a supply voltage of 1.8 V, and occupying a silicon area around 0:010mm2. Results from circuit simulation show an TCeff of 60 ppm/oC from -45 to +85 oC and a power consumption of 63 W. The first proposed voltage reference is an EMI Resisting MOSFET-Only Voltage Reference (EMIVR), which generates a voltage reference of 395 mV. The circuit is designed in a 130 nm process, occupying around 0.0075 mm2 of silicon area while consuming just 10.3 W. Post-layout simulations present a TCeff of 146 ppm/oC, for a temperature range from 55 to +125oC. An EMI source of 4 dBm (1 Vpp amplitude) injected into the power supply of circuit, according to Direct Power Injection (DPI) specification results in a maximum DC Shift and Peak-to-Peak ripple of -1.7 % and 35.8m Vpp, respectively. The second proposed voltage reference is a 0.5V Schottky-based Voltage Reference (SBVR). It provides three voltage reference outputs, each one utilizing different threshold voltage MOSFETs (standard-VT , low-VT , and zero-VT ), all available in adopted 130 nm CMOS process. This design results in three different and very low reference voltages: 312, 237, and 51 mV, presenting a TCeff of 214, 372, and 953 ppm/oC in a temperature range from -55 to 125oC, respectively. It occupies around 0.014 mm2 of silicon area for a total power consumption of 5.9 W. Lastly, a few example Gm-C circuits are designed using GZTC technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits are simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.A contínua miniaturização das tecnologias CMOS oferece maior capacidade de integração e, consequentemente, as variações de temperatura dentro de uma pastilha de silício têm se apresentado cada vez mais agressivas. Ademais, dependendo da aplicação, a temperatura ambiente a qual o CHIP está inserido pode variar. Dessa maneira, procedimentos para diminuir o impacto dessas variações no desempenho do circuito são imprescindíveis. Tais métodos devem ser incluídos em ambos fluxos de projeto CMOS, analógico e digital, de maneira que o desempenho do sistema se mantenha estável quando a temperatura oscilar. A ideia principal desta dissertação é propor uma metodologia de projeto CMOS analógico que possibilite circuitos com baixa dependência térmica. Como base fundamental desta metodologia, o efeito de coeficiente térmico nulo no ponto de polarização da corrente de dreno (ZTC) e da transcondutância (GZTC) do MOSFET são analisados e modelados. Tal modelamento é responsável por entregar ao projetista analógico um conjunto de equações que esclarecem como a temperatura influencia o comportamento do transistor e, portanto, o comportamento do circuito. Essas condições especiais de polarização são analisadas usando um modelo de MOSFET que é contínuo da inversão fraca para forte. Além disso, é mostrado que as duas condições ocorrem em inversão moderada para forte em qualquer processo CMOS. Algumas aplicações são projetadas usando a metodologia proposta: duas referências de corrente baseadas em ZTC, duas referências de tensão baseadas em ZTC, e quatro circuitos gm-C polarizados em GZTC. A primeira referência de corrente é uma Corrente de Referência CMOS Auto-Polarizada (ZSBCR), que gera uma referência de 5uA. Projetada em CMOS 180 nm, a referência opera com uma tensão de alimentação de 1.4 à 1.8 V, ocupando uma área em torno de 0:010mm2. Segundo as simulações, o circuito apresenta um coeficiente de temperatura efetivo (TCeff ) de 15 ppm/oC para -45 à +85 oC e uma sensibilidade à variação de processo de = = 4:5% incluindo efeitos de variabilidade dos tipos processo e descasamento local. A sensibilidade de linha encontrada nas simulações é de 1%=V . A segunda referência de corrente proposta é uma Corrente de Referência Sem Resistor Auto-Polarizada com Capacitor Chaveado (ZSCCR). O circuito é projetado também em 180 nm, resultando em uma corrente de referência de 5.88 A, para uma tensão de alimentação de 1.8 V, e ocupando uma área de 0:010mm2. Resultados de simulações mostram um TCeff de 60 ppm/oC para um intervalo de temperatura de -45 à +85 oC e um consumo de potência de 63 W. A primeira referência de tensão proposta é uma Referência de Tensão resistente à pertubações eletromagnéticas contendo apenas MOSFETs (EMIVR), a qual gera um valor de referência de 395 mV. O circuito é projetado no processo CMOS 130 nm, ocupando em torno de 0.0075 mm2 de área de silício, e consumindo apenas 10.3 W. Simulações pós-leiaute apresentam um TCeff de 146 ppm/oC, para um intervalo de temperatura de 55 à +125oC. Uma fonte EMI de 4 dBm (1 Vpp de amplitude) aplicada na alimentação do circuito, de acordo com o padrão Direct Power Injection (DPI), resulta em um máximo de desvio DC e ondulação Pico-à-Pico de -1.7 % e 35.8m Vpp, respectivamente. A segunda referência de tensão é uma Tensão de Referência baseada em diodo Schottky com 0.5V de alimentação (SBVR). Ela gera três saídas, cada uma utilizando MOSFETs com diferentes tensões de limiar (standard-VT , low-VT , e zero-VT ). Todos disponíveis no processo adotado CMOS 130 nm. Este projeto resulta em três diferentes voltages de referências: 312, 237, e 51 mV, apresentando um TCeff de 214, 372, e 953 ppm/oC no intervalo de temperatura de -55 à 125oC, respectivamente. O circuito ocupa em torno de 0.014 mm2, consumindo um total de 5.9 W. Por último, circuitos gm-C são projetados usando o conceito GZTC: um emulador de resistor, um inversor de impedância, um filtro de primeira ordem e um filtro de segunda ordem. Os circuitos também são simulados no processo CMOS 130 nm, resultando em uma melhora na estabilidade térmica dos seus principais parâmetros, indo de 27 à 53 ppm/°C

Conception, fabrication et caractérisation de diodes Schottky planaires terahertz

Dans cette thèse, les diodes Schottky pour des applications en ondes millimétriques et aux fréquences térahertz sont étudiées. Une méthodologie de conception et d'optimisation est proposée pour améliorer la performance de telles diodes. La conception et les simulations sont effectuées à l'aide d'un programme basé sur un modèle analytique. Les différentes méthodes de calcul de la fréquence de coupure de la diode sont définies, étudiées et classifiées selon les applications potentielles. En utilisant un modèle de diode générique et général, une nouvelle approche pour calculer la fréquence de coupure est suggérée pour les applications de mélangeur / multiplicateur. Cette approche permet d'évaluer la tension seuil avec une précision beaucoup plus grande et proche de la réalité. En outre, la conception d’une diode Schottky en tenant compte dès le départ l’application visée (détecteur direct, mélangeur ou multiplicateur) est étudiée. Cette thèse montre que l'ingénierie de la structure épitaxiale a un impact important lorsque l’on utilise une conception de diode basée sur l’application finale comme proposée. Un procédé de microfabrication a été entièrement développé et caractérisé. Une méthode de planarisation unique est introduite pour permettre de connecter la diode par des ponts à air en minimisant les effets parasites. Afin d'éviter une coûteuse lithographie par faisceau électronique, une anode en forme de T est produite en utilisant une technique de photolithographie. Ce procédé est fiable et répétitif, est de faible coût et offre une grande souplesse en matière de conception en plus de répondre au besoin d‘une production de masse, pour laquelle la lithographie par faisceau d’électrons n’est guère possible. Le procédé final nécessite simplement deux étapes de métallisation, nombre minimal possible que nous avons atteint. En raison des exigences de recuit du contact ohmique, il est impossible d’avoir moins de deux étapes de métallisation. Le processus de planarisation proposé repose sur l'utilisation de différents taux de gravure plasma de deux résines couramment utilisées. Pour les travaux réalisés dans cette thèse, une épitaxie GaAs HBT disponible au sein du laboratoire a été utilisée. Les résultats de caractérisation de diodes réalisés dérivés des mesures DC et RF sont rapportés et comparés avec les résultats de la simulation. Les résultats de mesure montrent une réduction significative de la capacité parasite de la diode à moins de 20% de sa capacité totale. Par conséquent, le procédé de conception et de fabrication de ce travail peut fournir des diodes qui peuvent fonctionner au-delà du térahertz avec des dimensions pour l’anode plus grandes que les diodes trouvées dans la littérature et qui peuvent donc être fabriquées uniquement par des techniques de photolithographie optique.Abstract: In this thesis, Schottky diodes for millimeter waves and terahertz application are scrutinized. A design and optimization methodology is proposed to improve the diode performance. Design and simulations are performed by using an analytical model based code. Diode cut-off frequency calculation methods are studied and classified for different applications. Considering general diode equivalent circuit model, a new approach for calculating the cut-off frequency is suggested for mixer/multiplier applications. This approach provides cut-off much closer to its practical value. Also, the diode design based on its application, direct detector and mixer/multiplier, is studied. It is shown that the epitaxial structure engineering has impact on diode application based design. For diode realization a microfabrication process is developed. Unique planarization method is introduced which provides necessary substruction for the airbridges. In order to avoid expensive e-beam lithography, a T-shaped anode is produced by employing photolithography technique. This process is repeatable, reliable, low cost, gives high flexibility in design terms, and suitable for mass production. The final process merely requires two metallization steps which is minimum possible number due to annealing requirement of ohmic contact. The proposed planarization process is based on using different plasma etching rates of two common resists. In the diode fabrication an available GaAs HBT epitaxial wafer is used. The realized diode characterization results derived from DC and RF measurements are reported and compared with the simulation results. The measurement results showed significant reduction in parasitic capacitance of the diode to under twenty percent of its total capacitance. Therefore, the design and fabrication method of this work can provide diodes to operate over one terahertz with larger anode area (that can be produced by photolithography techniques)

Modeling and Validation of 4H-SiC Low Voltage MOSFETs for Integrated Circuit Design

Silicon Carbide is a promising wide bandgap material and gradually becoming the first choice of semiconductor for high density and high efficiency power electronics in medium voltage range (500-1500V). SiC has also excellent thermal conductivity and the devices fabricated with the material can operate at high temperature (~ 400 ⁰C). Thus, a power electronic system built with SiC devices requires less cooling requirement and saves board space and cost. The high temperature applications of SiC material can also be extended to space exploration, oil and gas rigging, aerospace and geothermal energy systems for data acquisition, sensing and instrumentation and power conditioning and conversion. But the high temperature capability of SiC can only be utilized when the integrated circuits can be designed in SiC technology and high fidelity compact models of the semiconductor devices are a priori for reliable and high yielding integrated circuit design. The objective of this work is to develop industry standard compact models for SiC NMOS and PMOS devices. A widely used compact model used in silicon industry called BSIM3V3 is adopted as a foundation to build the model for SiC MOSFET. The models optimized with the built-in HSPICE BSIM3V3.3 were used for circuit design in one tape-out but BSIM3V3 was found to be inadequate to model all of the characteristics of SiC MOSFET due to the presence of interface trapped charge. In the second tape-out, the models for SiC NMOS and PMOS were optimized based on the built-in HSPICE BSIM4V6.5 and a number of functioning circuits which have been published in reputed journal and conference were designed based on the models. Although BSIM4 is an enhanced version of BSIM3V3, it also could not model a few deviant SiC MOSFET characteristics such as body effect, soft saturation etc. The new model developed for SiC NMOS and PMOS based on BSIM4V7.0 is called BSIM4SIC and can model the entire range of device characteristics of the devices. The BSIM4SIC models are validated with a wide range of measured data and verified using the models in the simulation of numerous circuits such as op-amp, comparator, linear regulator, reference and ADC/DAC

Critically coupled silicon Fabry-Perot photodetectors based on the internal photoemission effect at 1550 nm

In this paper, design, fabrication and characterization of an all-silicon photodetector (PD) at 1550 nm, have been reported. Our device is a surface-illuminated PD constituted by a Fabry-Perot microcavity incorporating a Cu/p-Si Schottky diode. Its absorption mechanism, based on the internal photoemission effect (IPE), has been enhanced by critical coupling condition. Our experimental findings prove a peak responsivity of 0.063 mA/W, which is the highest value obtained in a surface-illuminated IPE-based Si PD around 1550 nm. Finally, device capacitance measurements have been carried out demonstrating a capacitance < 5 pF which has the potential for GHz operation subject to a reduction of the series resistance of the ohmic contact

Ultra High Voltage IC design with a 400V CMOS technology: a dimmer application

The advent of Ultra High Voltage (UHV) technologies for integrated circuit fabrication opens up new possibilities for the design of circuits that connect directly to the power distribution network, with applications in the design of compact power sources, domotics, smart-grids, etc. This project proposes the design, fabrication and characterization of circuits in an UHV technology, of which a fully integrated two terminal phase-cut dimmer was chosen as an example. At the time of writing this thesis, no commercially available integrated circuit exists that fully implements a phase cut dimmer, and no academic papers could be found referencing similar circuits. The circuit was designed on a 1µm UHV MOS technology in a silicon-on-insulator (SOI) wafer (XDM10 from XFAB). The dimmer can operate with a duty cycle of up to 95% power (80% time) and a load of up to 100W which is adequate for modern domestic dimmable LED lights. The total occupied silicon area is 6.5mm2 without pads. Because of technological limitations, the final version of the dimmer is almost fully integrated. Two low voltage capacitors and four UHV diodes are outside the ASIC.Con la popularización de tecnologías de fabricación de circuitos integrados de ultra alto voltaje (UHV), surge la posibilidad de diseñar circuitos integrados conectados directamente a la red de distribución, con aplicaciones en fuentes compactas, domótica, smart-grids, entre otras. Este proyecto propone el diseño, fabricación y caracterización de circuitos en tecnología UHV. Se toma como ejemplo un atenuador por corte de fase de dos terminales. Al momento de escribir esta tesis, no existen circuitos integrados comerciales que implementan un atenuador por corte de fase completo, ni se pudo encontrar artículos académicos haciendo referencia a dispositivos similares. El circuito fue diseñado en una tecnología de 1µm UHV MOS (XDM10 de XFAB) en una oblea de silicio sobre aislante (SOI). Puede operar con un ciclo de trabajo hasta 95% de potencia (80% en tiempo) y una carga de hasta 100W, lo que es adecuado para lámparas atenuables de LED. El área total de silicio ocupada es de 6.5mm2 sin contar pads. Debido a limitaciones tecnológicas, la versión final del atenuador es casi completamente integrada. Dos capacitores de bajo voltaje y cuatro diodos UHV quedan por fuera del ASIC

4H-SiC Integrated circuits for high temperature and harsh environment applications

Silicon Carbide (SiC) has received a special attention in the last decades thanks to its superior electrical, mechanical and chemical proprieties. SiC is mostly used for applications where Silicon is limited, becoming a proper material for both unipolar and bipolar power device able to work under high power, high frequency and high temperature conditions. Aside from the outstanding theoretical and practical advantages still to be proved in SiC devices, the need for more accurate models for the design and optimization of these devices, along with the development of integrated circuits (ICs) on SiC is indispensable for the further success of modern power electronics. The design and development of SiC ICs has become a necessity since the high temperature operation of ICs is expected to enable important improvements in aerospace, automotive, energy production and other industrial systems. Due to the last impressive progresses in the manufacturing of high quality SiC substrates, the possibility of developing ICs applications is now feasible. SiC unipolar transistors, such as JFETs and MESFETs show a promising potential for digital ICs operating at high temperature and in harsh environments. The reported ICs on SiC have been realized so far with either a small number of elements, or with a low integration density. Therefore, this work demonstrates that by means of our SiC MESFET technology, multi-stage digital ICs fabrication containing a large number of 4H-SiC devices is feasible, accomplishing some of the most important ICs requirements. The ultimate objective is the development of SiC digital building blocks by transferring the Si CMOS topologies, hence demonstrating that the ICs SiC technology can be an important competitor of the Si ICs technology especially in application fields in which high temperature, high switching speed and harsh environment operations are required. The study starts with the current normally-on SiC MESFET CNM complete analysis of an already fabricated MESFET. It continues with the modeling and fabrication of a new planar-MESFET structure together with new epitaxial resistors specially suited for high temperature and high integration density. A novel device isolation technique never used on SiC before is approached. A fabrication process flow with three metal levels fully compatible with the CMOS technology is defined. An exhaustive experimental characterization at room and high temperature (300ºC) and Spice parameter extractions for both structures are performed. In order to design digital ICs on SiC with the previously developed devices, the current available topologies for normally-on transistors are discussed. The circuits design using Spice modeling, the process technology, the fabrication and the testing of the 4H-SiC MESFET elementary logic gates library at high temperature and high frequencies are performed. The MESFET logic gates behavior up to 300ºC is analyzed. Finally, this library has allowed us implementing complex multi-stage logic circuits with three metal levels and a process flow fully compatible with a CMOS technology. This study demonstrates that the development of important SiC digital blocks by transferring CMOS topologies (such as Master Slave Data Flip-Flop and Data-Reset Flip-Flop) is successfully achieved. Hence, demonstrating that our 4H-SiC MESFET technology enables the fabrication of mixed signal ICs capable to operate at high temperature (300ºC) and high frequencies (300kHz). We consider this study an important step ahead regarding the future ICs developments on SiC. Finally, experimental irradiations were performed on W-Schotthy diodes and mesa-MESFET devices (with the same Schottky gate than the planar SiC MESFET) in order to study their radiation hardness stability. The good radiation endurance of SiC Schottky-gate devices is proven. It is expected that the new developed devices with the same W-Schottky gate, to have a similar behavior in radiation rich environments.Postprint (published version