Linearized large signal modeling, analysis, and control design of phase-controlled series-parallel resonant converters using state feedback

This paper proposes a linearized large signal state-space model for the fixed-frequency phase-controlled series-parallel resonant converter. The proposed model utilizes state feedback of the output filter inductor current to perform linearization. The model combines multiple-frequency and average state-space modeling techniques to generate an aggregate model with dc state variables that are relatively easier to control and slower than the fast resonant tank dynamics. The main objective of the linearized model is to provide a linear representation of the converter behavior under large signal variation which is suitable for faster simulation and large signal estimation/calculation of the converter state variables. The model also provides insight into converter dynamics as well as a simplified reduced order transfer function for PI closed-loop design. Experimental and simulation results from a detailed switched converter model are compared with the proposed state-space model output to verify its accuracy and robustness

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI

This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC-DC switches, DC-DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices

Asynchronous Circuit Stacking for Simplified Power Management

As digital integrated circuits (ICs) continue to increase in complexity, new challenges arise for designers. Complex ICs are often designed by incorporating multiple power domains therefore requiring multiple voltage converters to produce the corresponding supply voltages. These converters not only take substantial on-chip layout area and/or off-chip space, but also aggregate the power loss during the voltage conversions that must occur fast enough to maintain the necessary power supplies. This dissertation work presents an asynchronous Multi-Threshold NULL Convention Logic (MTNCL) “stacked” circuit architecture that alleviates this problem by reducing the number of voltage converters needed to supply the voltage the ICs operate at. By stacking multiple MTNCL circuits between power and ground, supplying a multiple of VDD to the entire stack and incorporating simple control mechanisms, the dynamic range fluctuation problem can be mitigated. A 130nm Bulk CMOS process and a 32nm Silicon-on-Insulator (SOI) CMOS process are used to evaluate the theoretical effect of stacking different circuitry while running different workloads. Post parasitic physical implementations are then carried out in the 32nm SOI process for demonstrating the feasibility and analyzing the advantages of the proposed MTNCL stacking architecture

Modeling and Analysis of Power Processing Systems (MAPPS), initial phase 2

The overall objective of the program is to provide the engineering tools to reduce the analysis, design, and development effort, and thus the cost, in achieving the required performances for switching regulators and dc-dc converter systems. The program was both tutorial and application oriented. Various analytical methods were described in detail and supplemented with examples, and those with standardization appeals were reduced into computer-based subprograms. Major program efforts included those concerning small and large signal control-dependent performance analysis and simulation, control circuit design, power circuit design and optimization, system configuration study, and system performance simulation. Techniques including discrete time domain, conventional frequency domain, Lagrange multiplier, nonlinear programming, and control design synthesis were employed in these efforts. To enhance interactive conversation between the modeling and analysis subprograms and the user, a working prototype of the Data Management Program was also developed to facilitate expansion as future subprogram capabilities increase

Coordinated Control of Energy Storage in Networked Microgrids under Unpredicted Load Demands

In this paper a nonlinear control design for power balancing in networked microgrids using energy storage devices is presented. Each microgrid is considered to be interfaced to the distribution feeder though a solid-state transformer (SST). The internal duty cycle based controllers of each SST ensures stable regulation of power commands during normal operation. But problem arises when a sudden change in load or generation occurs in any microgrid in a completely unpredicted way in between the time instants at which the SSTs receive their power setpoints. In such a case, the energy storage unit in that microgrid must produce or absorb the deficit power. The challenge lies in designing a suitable regulator for this purpose owing to the nonlinearity of the battery model and its coupling with the nonlinear SST dynamics. We design an input-output linearization based controller, and show that it guarantees closed-loop stability via a cascade connection with the SST model. The design is also extended to the case when multiple SSTs must coordinate their individual storage controllers to assist a given SST whose storage capacity is insufficient to serve the unpredicted load. The design is verified using the IEEE 34-bus distribution system with nine SST-driven microgrids.Comment: 8 pages, 10 figure

Power Factor Corrector Design applied to an 85-kHz Wireless Charger

Wireless charging technology extends the battery autonomy by allowing more flexible and practical ways of recharging it even when the electric vehicle is on move. The frequency conversion, which is required to generate a kHz-ranged magnetic field, also leads to considerable harmonics. As a result, the power factor and the corresponding efficiency decrement. This paper proposes a Power Factor Corrector which overcomes this drawback. The most relevant feature of the designed Power Factor Corrector is that it does not need any electrical signal from the secondary side to adjust its operation properly. The simulation results show the ability of the proposed scheme to increment the system efficiency for different State-Of-Charge in the Battery.Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech

Per-Core DVFS with Switched-Capacitor Converters for Energy Efficiency in Manycore Processors

Integrating multiple power converters on-chip improves energy efficiency of manycore architectures. Switched-capacitor (SC) dc-dc converters are compatible with conventional CMOS processes, but traditional implementations suffer from limited conversion efficiency. We propose a dynamic voltage and frequency scaling scheme with SC converters that achieves high converter efficiency by allowing the output voltage to ripple and having the processor core frequency track the ripple. Minimum core energy is achieved by hopping between different converter modes and tuning body-bias voltages. A multicore processor model based on a 28-nm technology shows conversion efficiencies of 90% along with over 25% improvement in the overall chip energy efficiency

Development and implementation of a LabVIEW based SCADA system for a meshed multi-terminal VSC-HVDC grid scaled platform

This project is oriented to the development of a Supervisory, Control and Data Acquisition (SCADA) software to control and supervise electrical variables from a scaled platform that represents a meshed HVDC grid employing National Instruments hardware and LabVIEW logic environment. The objective is to obtain real time visualization of DC and AC electrical variables and a lossless data stream acquisition. The acquisition system hardware elements have been configured, tested and installed on the grid platform. The system is composed of three chassis, each inside of a VSC terminal cabinet, with integrated Field-Programmable Gate Arrays (FPGAs), one of them connected via PCI bus to a local processor and the rest too via Ethernet through a switch. Analogical acquisition modules were A/D conversion takes place are inserted into the chassis. A personal computer is used as host, screen terminal and storing space. There are two main access modes to the FPGAs through the real time system. It has been implemented a Scan mode VI to monitor all the grid DC signals and a faster FPGA access mode VI to monitor one converter AC and DC values. The FPGA application consists of two tasks running at different rates and a FIFO has been implemented to communicate between them without data loss. Multiple structures have been tested on the grid platform and evaluated, ensuring the compliance of previously established specifications, such as sampling and scanning rate, screen refreshment or possible data loss. Additionally a turbine emulator was implemented and tested in Labview for further testing

Sensorless multi-loop control of phase-controlled series-parallel resonant converter

This paper proposes a multi-loop controller for the phase-controlled series-parallel resonant converter. Output voltage is solely measured for control and inner loop is used to enhance closed loop stability and dynamic performance compared to single-loop control. No additional sensors are used for inner loop variables. These are estimated using a Kalman filter, based on a linearized converter model. The advantage of this sensorless scheme is not only reducing the number of sensors but more significantly providing an alternative to sensing high frequency resonant tank variables which require high microcontroller resolution in real time. First, the converter non-linear large signal behavior is linearized using a state feedback based scheme. Consequently, the converter preserves its large signal characteristics while modeled as a linear system. Comparison is made between the most suitable state variables for feedback, according to a stability study. Finally, simulation and experimental results are demonstrated to validate the improved system performance in contrast with single-loop control