Experimental Comparison of Store-and-Forward and Wormhole NoC Routers for FPGA\u27s

Network on Chip (NoC) is an interconnection paradigm which is scalable and efficient for connecting increasing number of components on Field Programmable Systems on Chip (FPSOC). The router is a key component in NoC that impacts area performance, power consumption, etc. In this thesis we evaluate and compare two different router designs using real world benchmark. The first router uses Store-And-Forward strategy (SAF) and XY routing algorithm and the second router uses Wormhole (WH) as forwarding strategy and source routing algorithm. These routers were used to implement 4x4 mesh NoCs. A multi processor system benchmark obtained from Altera was implemented in each NoC. This enabled us to evaluate and compare the routers using the real world benchmark design. The evaluation metrics used were area, throughput, power consumption and maximum clock frequency. Experiment results show that the SAF router is superior to the WH Router

NoC Prototyping on FPGAs: Component Design, Architecture Implementation and Comparison

Continuing improvements in integrated circuit technology over the past few decades enables increasingly large and complex Systems-on-Chip. Due to the large number of components used, the traditional bus-based interconnect scheme becomes cumbersome and restrictive. Hence, the Network-on-Chip interconnect paradigm becomes appealing due to its many advantages such as scalability and superior performance. Much research remains to be done exploring NoC architectures using real world benchmarks. In this thesis we describe the design space exploration of two major NoC components; a flexible adapter based on the Altera Avalon standard and a parameterizable wormhole router. Two well known NoC architectures, torus and ring, were synthesized for Altera FPGAs using these NoC components. The architectures were compared on the basis of packet latency, area and throughput, using a benchmark application. Simulation results show that the ring architecture gives superior area versus performance tradeoffs for the benchmark used

Experimental Evaluation of an NoC Synthesis Tool

Rapid growth in the number of IP cores in SoCs resulted in the need for effective and scalable interconnect scheme for system components - Network-on-Chip (NoC). Design and implementation of an NoC from scratch is very time consuming and limits the NoC design space that can be explored. In this thesis we evaluate and compare NoC synthesis tool CONNECT with manually generated NoC design using Altera Quartus II. Three sizes of ring, mesh and torus NoC topologies are used for evaluation based on two metrics: logic resource utilization and maximum clock frequency. For larger NoC sizes manual design provides up to 85% reduction in area utilization. With respect to maximum clock frequency, CONNECT provides superior results for all NoC sizes, providing up to 80% higher clock frequency. These results provide an insight into the area versus frequency tradeoffs when using the CONNECT NoC synthesis tool