Fortschrittliche Detektions-und Entfernungsmethode von Polymerrückständen in Through Silicon Vias (TSV)

With conventional planar monolithic integrated circuit designs approaching their limits, emerging 3D integration technology is enabling higher levels of performance and functionality using through-silicon vias (TSVs) for vertical interconnections. The basic TSV manufacturing process consists of four major components: formation, isolation, metallization, and passivation. Polymer contaminations formed inside the TSVs during processing can cause delamination of deposited metal and isolation layers, resulting in an immediate or delayed electrical failure of the device. The post-etch polymer removal process usually consists of a wet and dry cleaning sequence, which prepares the wafer surface for subsequent material deposition. With increasing aspect ratios, removal and inspection of the sidewall polymer residue are becoming increasingly difficult. The first goal of this thesis is to develop a cleaning evaluation method for TSVs after a wet-chemical cleaning that follows a through-spacer-oxide etching step (TSE). Special attention should be paid to the adaption to shrinking dimensions, reduction of the inspection duration, and specimen preparation complexity. Secondly, this thesis intends to formulate an improved cleaning method for a dry or wet cleaning subsequent to a TSE. The new or extended cleaning method should also be adaptable to shrinking dimensions, as well as reduce the cleaning duration compared to previous cleaning times. As part of a co-operation between the ams AG and FhG IISB, both a novel TSV wafer cleaning process evaluation method, as well as a cleaning method have been developed. Both methods have been experimentally investigated on the base of TSVs that have been processed up to and including the TSE. For each of these methods, wafers with specific TSV sizes, or rather specific aspect ratios (AR 1:5 and 1:2.5), have been provided by ams AG. For an accurate wafer cleaning evaluation, a new method for sidewall polymer residue detection inside the TSVs has been developed. In general, this method is based on labelling of the sidewall polymers with fluorophores. Due to polymer material characteristics, the small interaction volume, and the location of polymer residue, many of the conventional labelling methods such as chemical or physical activation of the polymer surface cannot be used. For this reason, the newly-developed polymer detection method operates with supercritical CO2 and its diffusion into the polymer matrix. To this end, an innovative laboratory autoclave has been designed and constructed. The residual polymers are labelled by means of impregnation with fluorophores, which are transported into the polymer matrix with CO2 as a carrier. A non-destructive examination under a confocal laser scanning microscope (CLSM) detects the existence and location of residue. This novel optical detection method, based on fluorophore pressure impregnation, circumvents the drawbacks of destructive analysis methods and provides an efficient and reproducible procedure to detect polymer residue on wafer-level. The second part of this thesis involves the development of a novel TSV sidewall polymer stripping method. This method, tested within different TSV aspect ratios following a TSE, consists of a dry and a wet-chemical cleaning, and is based on knowledge gained from fluorophore pressure impregnation experiments and on extended state-of-the art wet cleaning procedures. In accordance with the experimental results, TSV surface wetting behaviour, polymer stripping mechanism, and the influence of CO2 on polymer residue are discussed. With the novel sidewall polymer stripping method, a total cleaning with reduced cleaning process time for TSVs after the TSE has been realized. One of the primary findings of this research is that supercritical CO2 can be applied to polymer detection as well as to TSV cleaning processes. Characteristics such as non-toxicity, non-apparent wafer material interactions, operational simplicity, and competitive price have made CO2 attractive to the semiconductor manufacturing industry for many years. While CO2 will presumably not replace the complete wet cleaning chemistry in wafer cleaning technology, due to its many advantages it will likely reduce the cleaning agents to a minimum

Design of Readout Electronics for the DEEP Particle Detector

Along with electromagnetic radiation, the Sun also emits a constant stream of charged particles in the form of solar wind. When these particles enter Earth’s atmosphere through a process known as particle precipitation, they can through a series of chemical reactions produce N Ox and HOx gases. These gases are greenhouse gases and deplete the ozone in the mesosphere and upper stratosphere. It is important to quantify the rate of production of these gases to model the potential climate impact. Existing particle detectors in space are suboptimal because they cannot determine the energy flux and pitch angle distribution of precipitating particles. The primary scientific objective of the DEEP project is to design a particle detector instrument that is specifically designed for particle precipitation measurements. This thesis investigates different data acquisition schemes for handling the signal from a pixel detector. The chosen approach is measuring the width of a shaped pulse to quantify the energy of the particle. Known as Time-over-Threshold, a detector circuit board is designed featuring high-speed comparators as threshold discriminators and the NG-MEDIUM FPGA from NanoXplore to implement the data acquisition. Digitizing the comparator pulse width is done with a Time-to-Digital converter (TDC) implemented in the FPGA fabric. Since the difference in pulse width is small for different energies, a high conversion resolution is required. Two high-resolution TDCs are designed and compared, both of which feature a digital counter and a method of interpolating the counter clock period. The first interpolation method applies the use of a multitapped delay line implemented with hard carry chain resources, and the second method oversamples the input with several equally off-phase sampling clocks. A resolution of 302 ps and a differential non-linearity of 3.26 was achieved with the delay line TDC clocked at 100 MHz. An automatic statistical calibration scheme is included to determine the actual delays of the delay line, utilizing a second asynchronous clock to generate uniformly distributed hits. The asynchronous oversampler resolution is clock frequency dependent and provides a 4-fold improvement to the clock period. The differential nonlinearity approaches zero with close matching of the off-phase clocks and operating frequency. A complete firmware design for the data acquisition and rocket telemetry of the detector is proposed and demonstrated. A simulation of the firmware utilizing each TDC topology is conducted and the delay line TDC is demonstrated to be the most accurate at all operating frequencies and thus the recommended TDC for the DEEP data acquisition.Masteroppgave i fysikkPHYS399MAMN-PHY

Design and optimization of approximate multipliers and dividers for integer and floating-point arithmetic

The dawn of the twenty-first century has witnessed an explosion in the number of digital devices and data. While the emerging deep learning algorithms to extract information from this vast sea of data are becoming increasingly compute-intensive, traditional means of improving computing power are no longer yielding gains at the same rate due to the diminishing returns from traditional technology scaling. To minimize the increasing gap between computational demands and the available resources, the paradigm of approximate computing is emerging as one of the potential solutions. Specifically, the resource-efficient approximate arithmetic units promise overall system efficiency, since most of the compute-intensive applications are dominated by arithmetic operations. This thesis primarily presents design techniques for approximate hardware multipliers and dividers. The thesis presents the design of two approximate integer multipliers and an approximate integer divider. These are: an error-configurable minimally-biased approximate integer multiplier (MBM), an error-configurable reduced-error approximate log based multiplier (REALM), and error-configurable integer divider INZeD. The two multiplier designs and the divider designs are based on the coupling of novel mathematically formulated error-reduction mechanisms in the classical approximate log based multiplier and dividers, respectively. They exhibit very low error bias and offer Pareto-optimal error vs. resource-efficiency trade-offs when compared with the state-of-the-art approximate integer multipliers/dividers. Further, the thesis also presents design of approximate floating-point multipliers and dividers. These designs utilize the optimized versions of the proposed MBM and REALM multipliers for mantissa multiplications and the proposed INZeD divider for mantissa division, and offer better design trade-offs than traditional precision scaling. The existing approximate integer dividers as well as the proposed INZeD suffer from unreasonably high worst-case error. This thesis presents WEID, which is a novel light-weight method for reducing worst-case error in approximate dividers. Finally, the thesis presents a methodology for selection of approximate arithmetic units for a given application. The methodology is based on a novel selection algorithm and utilizes the subrange error characterization of approximate arithmetic units, which performs error characterization independently in different segments of the input range

Tuning the Computational Effort: An Adaptive Accuracy-aware Approach Across System Layers

This thesis introduces a novel methodology to realize accuracy-aware systems, which will help designers integrate accuracy awareness into their systems. It proposes an adaptive accuracy-aware approach across system layers that addresses current challenges in that domain, combining and tuning accuracy-aware methods on different system layers. To widen the scope of accuracy-aware computing including approximate computing for other domains, this thesis presents innovative accuracy-aware methods and techniques for different system layers. The required tuning of the accuracy-aware methods is integrated into a configuration layer that tunes the available knobs of the accuracy-aware methods integrated into a system