Using ultra-thin parylene films as an organic gate insulator in nanowire field-effect transistors

We report the development of nanowire field-effect transistors featuring an ultra-thin parylene film as a polymer gate insulator. The room temperature, gas-phase deposition of parylene is an attractive alternative to oxide insulators prepared at high temperatures using atomic layer deposition. We discuss our custom-built parylene deposition system, which is designed for reliable and controlled deposition of <100 nm thick parylene films on III-V nanowires standing vertically on a growth substrate or horizontally on a device substrate. The former case gives conformally-coated nanowires, which we used to produce functional $\Omega$-gate and gate-all-around structures. These give sub-threshold swings as low as 140 mV/dec and on/off ratios exceeding $10^3$ at room temperature. For the gate-all-around structure, we developed a novel fabrication strategy that overcomes some of the limitations with previous lateral wrap-gate nanowire transistors. Finally, we show that parylene can be deposited over chemically-treated nanowire surfaces; a feature generally not possible with oxides produced by atomic layer deposition due to the surface `self-cleaning' effect. Our results highlight the potential for parylene as an alternative ultra-thin insulator in nanoscale electronic devices more broadly, with potential applications extending into nanobioelectronics due to parylene's well-established biocompatible properties

An investigation of the effects of radiation on silicon nitride insulated gate /MNS/ transistors Final report

Radiation effects on silicon nitride insulated gate field effect transistor

Performance of a spin-based insulated gate field effect transistor

Fundamental physical properties limiting the performance of spin field effect transistors are compared to those of ordinary (charge-based) field effect transistors. Instead of raising and lowering a barrier to current flow these spin transistors use static spin-selective barriers and gate control of spin relaxation. The different origins of transistor action lead to distinct size dependences of the power dissipation in these transistors and permit sufficiently small spin-based transistors to surpass the performance of charge-based transistors at room temperature or above. This includes lower threshold voltages, smaller gate capacitances, reduced gate switching energies and smaller source-drain leakage currents.Comment: 4 pages including 3 figures, APL in pres

Field-effect transistors as dc amplifiers

Field effect transistors as direct current amplifier

An introduction to the BANNING design automation system for shuttle microelectronic hardware development

The BANNING MOS design system is presented. It complements rather than supplant the normal design activities associated with the design and fabrication of low-power digital electronic equipment. BANNING is user-oriented and requires no programming experience to use effectively. It provides the user a simulation capability to aid in his circuit design and it eliminates most of the manual operations involved in the layout and artwork generation of integrated circuits. An example of its operation is given and some additional background reading is provided

Microelectromechanical Systems (MEMS) Resistive Heaters as Circuit Protection Devices

With increased opportunities for the exploitation (i.e., reverse engineering) of vulnerable electronic components and systems, circuit protection has become a critical issue. Circuit protection techniques are generally software-based and include cryptography (encryption/decryption), obfuscation of codes, and software guards. Examples of hardware-based circuit protection include protective coatings on integrated circuits, trusted foundries, and macro-sized components that self-destruct, thus destroying critical components. This paper is the first to investigate the use of microelectromechanical systems (MEMS) to provide hardware-based protection of critical electronic components to prevent reverse engineering or other exploitation attempts. Specifically, surface-micromachined polycrystalline silicon to be used as meandering resistive heaters were designed analytically and fabricated using a commercially available MEMS prototyping service (i.e., PolyMUMPs), and integrated with representative components potentially at risk for exploitation, in this case pseudomorphic high-electron mobility transistors (pHEMTs). The MEMS heaters were initiated to self-destruct, destroying a critical circuit component and thwart a reverse engineering attempt. Tests revealed reliable self-destruction of the MEMS heaters with approximately 25 V applied, resulting in either complete operational failure or severely altering the pHEMT device physics. The prevalent failure mechanism was metallurgical, in that the material on the surface of the device was changed, and the specific failure mode was the creation of a short-circuit. Another failure mode was degraded device operation due to permanently altered device physics related to either dopant diffusion or ohmic contact degradation. The results, in terms of the failure of a targeted electronic component, demonstrate the utility of using MEMS devices to protect critical components which are otherwise vulnerable to exploitation

A sub-critical barrier thickness normally-off AlGaN/GaN MOS-HEMT

A new high-performance normally-off gallium nitride (GaN)-based metal-oxide-semiconductor high electron mobility transistor that employs an ultrathin subcritical 3 nm thick aluminium gallium nitride (Al0.25Ga0.75N) barrier layer and relies on an induced two-dimensional electron gas for operation is presented. Single finger devices were fabricated using 10 and 20 nm plasma-enhanced chemical vapor-deposited silicon dioxide (SiO2) as the gate dielectric. They demonstrated threshold voltages (Vth) of 3 and 2 V, and very high maximum drain currents (IDSmax) of over 450 and 650 mA/mm, at a gate voltage (VGS) of 6 V, respectively. The proposed device is seen as a building block for future power electronic devices, specifically as the driven device in the cascode configuration that employs GaN-based enhancement-mode and depletion-mode devices

Carrier Transport in High Mobility InAs Nanowire Junctionless Transistors

Ability to understand and model the performance limits of nanowire transistors is the key to design of next generation devices. Here, we report studies on high-mobility junction-less gate-all-around nanowire field effect transistor with carrier mobility reaching 2000 cm2/V.s at room temperature. Temperature-dependent transport measurements reveal activated transport at low temperatures due to surface donors, while at room temperature the transport shows a diffusive behavior. From the conductivity data, the extracted value of sound velocity in InAs nanowires is found to be an order less than the bulk. This low sound velocity is attributed to the extended crystal defects that ubiquitously appear in these nanowires. Analyzing the temperature-dependent mobility data, we identify the key scattering mechanisms limiting the carrier transport in these nanowires. Finally, using these scattering models, we perform drift-diffusion based transport simulations of a nanowire field-effect transistor and compare the device performances with experimental measurements. Our device modeling provides insight into performance limits of InAs nanowire transistors and can be used as a predictive methodology for nanowire-based integrated circuits.Comment: 22 pages, 5 Figures, Nano Letter