Design and analysis of a scalable terabit multicast packet switch : architecture and scheduling algorithms

Internet growth and success not only open a primary route of information exchange for millions of people around the world, but also create unprecedented demand for core network capacity. Existing switches/routers, due to the bottleneck from either switch architecture or arbitration complexity, can reach a capacity on the order of gigabits per second, but few of them are scalable to large capacity of terabits per second. In this dissertation, we propose three novel switch architectures with cooperated scheduling algorithms to design a terabit backbone switch/router which is able to deliver large capacity, multicasting, and high performance along with Quality of Service (QoS). Our switch designs benefit from unique features of modular switch architecture and distributed resource allocation scheme. Switch I is a unique and modular design characterized by input and output link sharing. Link sharing resolves output contention and eliminates speedup requirement for central switch fabric. Hence, the switch architecture is scalable to any large size. We propose a distributed round robin (RR) scheduling algorithm which provides fairness and has very low arbitration complexity. Switch I can achieve good performance under uniform traffic. However, Switch I does not perform well for non-uniform traffic. Switch II, as a modified switch design, employs link sharing as well as a token ring to pursue a solution to overcome the drawback of Switch 1. We propose a round robin prioritized link reservation (RR+POLR) algorithm which results in an improved performance especially under non-uniform traffic. However, RR+POLR algorithm is not flexible enough to adapt to the input traffic. In Switch II, the link reservation rate has a great impact on switch performance. Finally, Switch III is proposed as an enhanced switch design using link sharing and dual round robin rings. Packet forwarding is based on link reservation. We propose a queue occupancy based dynamic link reservation (QOBDLR) algorithm which can adapt to the input traffic to provide a fast and fair link resource allocation. QOBDLR algorithm is a distributed resource allocation scheme in the sense that dynamic link reservation is carried out according to local available information. Arbitration complexity is very low. Compared to the output queued (OQ) switch which is known to offer the best performance under any traffic pattern, Switch III not only achieves performance as good as the OQ switch, but also overcomes speedup problem which seriously limits the OQ switch to be a scalable switch design. Hence, Switch III would be a good choice for high performance, scalable, large-capacity core switches

Multicast cross-path ATM switches: principles, designs and performance evaluations.

by Lin Hon Man.Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.Includes bibliographical references (leaves 59-[63]).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Organization of Thesis --- p.3Chapter 2 --- Principles of Multicast Cross-Path Switches --- p.4Chapter 2.1 --- Introduction --- p.4Chapter 2.2 --- Unicast Cross-Path switch --- p.5Chapter 2.2.1 --- Routing properties in Clos networks --- p.5Chapter 2.2.2 --- Quasi-static routing procedures --- p.5Chapter 2.2.3 --- Capacity and Route Assignment --- p.7Chapter 2.3 --- Multicast Cross-Path Switch --- p.8Chapter 2.3.1 --- Scheme 1 - Cell replication performed at both input and output stages --- p.10Chapter 2.3.2 --- Scheme 2 - Cell replication performed only at the input stage --- p.10Chapter 3 --- Architectures --- p.14Chapter 3.1 --- Introduction --- p.14Chapter 3.2 --- Input Module Design (Scheme 1) --- p.16Chapter 3.2.1 --- Input Header Translator --- p.16Chapter 3.2.2 --- Input Module Controller --- p.17Chapter 3.2.3 --- Input Replication Network (Scheme 1) --- p.19Chapter 3.2.4 --- Routing Network --- p.23Chapter 3.3 --- Central Modules --- p.24Chapter 3.4 --- Output Module Design (Scheme 1) --- p.24Chapter 3.5 --- Input Module Design (Scheme 2) --- p.25Chapter 3.5.1 --- Input Header Translator (Scheme 2) --- p.26Chapter 3.5.2 --- Input Module Controller (Scheme 2) --- p.27Chapter 3.5.3 --- Input Replication Network (Scheme 2) --- p.28Chapter 3.6 --- Output Module Design (Scheme 2) --- p.29Chapter 4 --- Performance Evaluations --- p.31Chapter 4.1 --- Introduction --- p.31Chapter 4.2 --- Traffic characteristics --- p.31Chapter 4.2.1 --- Fanout distribution --- p.31Chapter 4.2.2 --- Middle stage traffic load and its calculation --- p.32Chapter 4.3 --- Throughput Performance --- p.34Chapter 4.4 --- Delay Performance --- p.37Chapter 4.4.1 --- Input Stage Delay --- p.38Chapter 4.4.2 --- Output Stage Delay --- p.39Chapter 4.5 --- Cell Loss Performance --- p.43Chapter 4.5.1 --- Cell Loss due to Buffer Overflow --- p.44Chapter 4.5.2 --- Cell Loss Due to Output Contention --- p.45Chapter 4.6 --- Complexities --- p.50Chapter 5 --- Conclusions --- p.57Bibliography --- p.5

Isochronets: a High-Speed Network Switching Architecture

Traditional switching techniques need hundred- or thousand-MIPS processing power within switches to support Gbit/s transmission rates available today. These techniques anchor their decision-making on control information within transmitted frames and thus must resolve routes at the speed in which frames are being pumped into switches. Isochronets can potentially switch at any transmission rate by making switching decisions independent of frame contents. Isochronets divide network bandwidth among routing trees, a technique called Route Division Multiple Access (RDMA). Frames access network resources through the appropriate routing tree to the destination. Frame structures are irrelevant for switching decisions. Consequently, Isochronets can support multiple framing protocols without adaptation layers and are strong candidates for all-optical implementations. All network-layer functions are reduced to an admission control mechanism designed to provide quality of service (QOS) guarantees for multiple classes of traffic. The main results of this work are: (1) A new network architecture suitable for high-speed transmissions; (2) An implementation of Isochronets using cheap off-theshelf components; (3) A comparison of RDMA with more traditional switching techniques, such as Packet Switching and Circuit Switching; (4) New protocols necessary for Isochronet operations; and (5) Use of Isochronet techniques at higher layers of the protocol stack (in particular, we show how Isochronet techniques may solve routing problems in ATM networks)

Switching techniques for broadband ISDN

The properties of switching techniques suitable for use in broadband networks have been investigated. Methods for evaluating the performance of such switches have been reviewed. A notation has been introduced to describe a class of binary self-routing networks. Hence a technique has been developed for determining the nature of the equivalence between two networks drawn from this class. The necessary and sufficient condition for two packets not to collide in a binary self-routing network has been obtained. This has been used to prove the non-blocking property of the Batcher-banyan switch. A condition for a three-stage network with channel grouping and link speed-up to be nonblocking has been obtained, of which previous conditions are special cases. A new three-stage switch architecture has been proposed, based upon a novel cell-level algorithm for path allocation in the intermediate stage of the switch. The algorithm is suited to hardware implementation using parallelism to achieve a very short execution time. An array of processors is required to implement the algorithm The processor has been shown to be of simple design. It must be initialised with a count representing the number of cells requesting a given output module. A fast method has been described for performing the request counting using a non-blocking binary self-routing network. Hardware is also required to forward routing tags from the processors to the appropriate data cells, when they have been allocated a path through the intermediate stage. A method of distributing these routing tags by means of a non-blocking copy network has been presented. The performance of the new path allocation algorithm has been determined by simulation. The rate of cell loss can increase substantially in a three-stage switch when the output modules are non-uniformly loaded. It has been shown that the appropriate use of channel grouping in the intermediate stage of the switch can reduce the effect of non-uniform loading on performance

Reconfiguration issues in a quasi-static packet switch.

by Man Wai-Hung.Thesis (M.Phil.)--Chinese University of Hong Kong, 2003.Includes bibliographical references (leaves 62-66).Abstracts in English and Chinese.Chapter 1 --- Introduction --- p.1Chapter 1.1 --- General Types of Switch Architecture --- p.2Chapter 1.1.1 --- Input-Buffered Switch --- p.2Chapter 1.1.2 --- Output-Buffered Switch --- p.4Chapter 1.1.3 --- Crossbar-Based Switch --- p.4Chapter 1.1.4 --- Shared Buffer Memory Switch --- p.5Chapter 1.2 --- From Clos Network to Cross-path Switch --- p.6Chapter 1.3 --- Motivation and Organization --- p.12Chapter 2 --- Route Reconfiguration in Clos Network --- p.14Chapter 2.1 --- Connection Matrix in Clos Network --- p.15Chapter 2.2 --- Rearranging Central Modules in Clos Network --- p.18Chapter 2.3 --- Changing the Connection Matrix --- p.20Chapter 2.4 --- One Step Route Reconfiguration --- p.21Chapter 2.5 --- Closing Remarks --- p.25Chapter 3. --- Frame-Based Reconfiguration Scheme in Cross-Path Switch --- p.26Chapter 3.1 --- Route Assignment in Cross-Path Switch --- p.27Chapter 3.1.1 --- Requirement Matrix and Capacity Matrix --- p.27Chapter 3.1.2 --- Allocation Vector --- p.29Chapter 3.2 --- Progress Tracing in Cross-Path Switch --- p.30Chapter 3.3 --- Implementing Frame-Based Reconfiguration --- p.32Chapter 3.3.1 --- Recognizing Receiver Virtual Path --- p.33Chapter 3.3.2 --- Finding Donor Virtual Path --- p.34Chapter 3.4 --- Simulation Results --- p.36Chapter 3.4.1 --- Fixed Requirement Matrix --- p.36Chapter 3.4.2 --- Time-Varying Requirement Matrix --- p.38Chapter 3.5 --- Unfavourable Reconfigurations --- p.39Chapter 3.6 --- Closing Remarks --- p.41Chapter 4. --- Performance and Delay Tradeoff in Frame-Based Reconfiguration Scheme --- p.43Chapter 4.1 --- Service Curve and Cross-Path Switch --- p.44Chapter 4.2 --- Service Curve of Cross-Path Switch under Reconfiguration --- p.45Chapter 4.3 --- Impact of Reconfiguration Algorithms to Maximum Delay Increase --- p.48Chapter 4.4 --- Numerical Example --- p.56Chapter 4.5 --- Closing Remarks --- p.57Chapter 5. --- Conclusions and Future Researches --- p.59Chapter 5.1 --- Suggestions for Future Researches --- p.60Bibliography --- p.6

Novel techniques in large scaleable ATM switches

Bibliography: p. 172-178.This dissertation explores the research area of large scale ATM switches. The requirements for an ATM switch are determined by overviewing the ATM network architecture. These requirements lead to the discussion of an abstract ATM switch which illustrates the components of an ATM switch that automatically scale with increasing switch size (the Input Modules and Output Modules) and those that do not (the Connection Admission Control and Switch Management systems as well as the Cell Switch Fabric). An architecture is suggested which may result in a scalable Switch Management and Connection Admission Control function. However, the main thrust of the dissertation is confined to the cell switch fabric. The fundamental mathematical limits of ATM switches and buffer placement is presented next emphasising the desirability of output buffering. This is followed by an overview of the possible routing strategies in a multi-stage interconnection network. A variety of space division switches are then considered which leads to a discussion of the hypercube fabric, (a novel switching technique). The hypercube fabric achieves good performance with an O(N.log₂N)²) scaling. The output module, resequencing, cell scheduling and output buffering technique is presented leading to a complete description of the proposed ATM switch. Various traffic models are used to quantify the switch's performance. These include a simple exponential inter-arrival time model, a locality of reference model and a self-similar, bursty, multiplexed Variable Bit Rate (VBR) model. FIFO queueing is simple to implement in an ATNI switch, however, more responsive queueing strategies can result in an improved performance. An associative memory is presented which allows the separate queues in the ATM switch to be effectively logically combined into a single FIFO queue. The associative memory is described in detail and its feasibility is shown by laying out the Integrated Circuit masks and performing an analogue simulation of the IC's performance is SPICE3. Although optimisations were required to the original design, the feasibility of the approach is shown with a 15Ƞs write time and a 160Ƞs read time for a 32 row, 8 priority bit, 10 routing bit version of the memory. This is achieved with 2µm technology, more advanced technologies may result in even better performance. The various traffic models and switch models are simulated in a number of runs. This shows the performance of the hypercube which outperforms a Clos network of equivalent technology and approaches the performance of an ideal reference fabric. The associative memory leverages a significant performance advantage in the hypercube network and a modest advantage in the Clos network. The performance of the switches is shown to degrade with increasing traffic density, increasing locality of reference, increasing variance in the cell rate and increasing burst length. Interestingly, the fabrics show no real degradation in response to increasing self similarity in the fabric. Lastly, the appendices present suggestions on how redundancy, reliability and multicasting can be achieved in the hypercube fabric. An overview of integrated circuits is provided. A brief description of commercial ATM switching products is given. Lastly, a road map to the simulation code is provided in the form of descriptions of the functionality found in all of the files within the source tree. This is intended to provide the starting ground for anyone wishing to modify or extend the simulation system developed for this thesis

Isochronets: A High-speed Network Switching Architecture

Traditional network architectures present two main limitations when applied to High- Speed Networks (HSNs): they do not scale with link speeds and they do not adequately support the Quality of Service (QoS) needs of high-performance applications. This thesis introduces the Isochronets architecture that overcomes both limitations. Isochronets view frame motions over links in analogy to motions on roads. In the latter, traffic lights can synchronize to create green waves of uninterrupted motion. Isochronets accomplish similar uninterrupted motion by periodically configuring network switches to create end-to-end routes in the network. Frames flow along these routes with no required header processing at intermediate switches. Isochronets offer several advantages. First, they are scaleable with respect to transmission speeds. Switches merely configure routes on a time scale that is significantly longer than and independent of the average frame transmission time. Isochronets do not require frame processing and thus avoid conversions from optical to electronic representations. They admit efficient optical transmissions under electronically controlled switches. Second, Isochronets ensure QoS for high-performance applications in terms of latency, jitter, loss, and other service qualities. Isochronet switches can give priority to frames arriving from selected links. At one extreme, they may give a source the right-of-way to the destination by assigning priority to all links in its path. Additionally, other sources may still transmit at lower priority. At the other extreme, they may give no priority to sources and frames en route to the same destination contend for intermediate links. In between, Isochronets can accomplish a myriad of priority allocations with diverse QoS. Third, Isochronets can support multiple protocols without adaptation between different frame structures. End nodes view the network as a media access layer that accepts frames of arbitrary structure. The main contributions of this thesis are: Design of the Isochronets architecture. Design and implementation of a gigabit per second Isochronet switch (Isoswitch). Definition of the Loosely-synchronous Transfer Mode (LTM) and the Synchronous Protocol Stack (SPS) that add synchronous and isochronous services to any existing protocol stack. Performance evaluation of Isochronets

Concentrators in ATM switching.

by Lau Chu Man.Thesis (M.Phil.)--Chinese University of Hong Kong, 1995.Includes bibliographical references (leaves 76-83).Chapter 1 --- Introduction --- p.1Chapter 2 --- Basic Notions --- p.13Chapter 3 --- Fast Knockout --- p.19Chapter 3.1 --- The Algorithm of Fast Knockout --- p.20Chapter 3.2 --- Complexity of the Fast Knockout Algorithm --- p.29Chapter 3.3 --- Summary --- p.35Chapter 4 --- k-Sortout --- p.36Chapter 4.1 --- A Brief Review of k-Sorting --- p.37Chapter 4.2 --- The Algorithm of k-Sortout --- p.47Chapter 4.3 --- Complexity of the k- Sortout Algorithm --- p.53Chapter 4.4 --- Summary --- p.58Chapter 5 --- General Sortout --- p.59Chapter 5.1 --- The General Algorithm of Sortout --- p.59Chapter 5.2 --- Complexity of Concentrators by the General Algorithm --- p.64Chapter 5.3 --- Summary --- p.69Chapter 6 --- Concluding Remarks --- p.70Chapter 6.1 --- Summary of Results --- p.70Chapter 6.2 --- Directions for Further Research --- p.73Bibliography --- p.7