3D IC optimal layout design. A parallel and distributed topological approach

The task of 3D ICs layout design involves the assembly of millions of components taking into account many different requirements and constraints such as topological, wiring or manufacturability ones. It is a NP-hard problem that requires new non-deterministic and heuristic algorithms. Considering the time complexity, the commonly applied Fiduccia-Mattheyses partitioning algorithm is superior to any other local search method. Nevertheless, it can often miss to reach a quasi-optimal solution in 3D spaces. The presented approach uses an original 3D layout graph partitioning heuristics implemented with use of the extremal optimization method. The goal is to minimize the total wire-length in the chip. In order to improve the time complexity a parallel and distributed Java implementation is applied. Inside one Java Virtual Machine separate optimization algorithms are executed by independent threads. The work may also be shared among different machines by means of The Java Remote Method Invocation system.Comment: 26 pages, 9 figure

Network partitioning into tree hierarchies

This paper addresses the problem of partitioning a circuit into a tree hierarchy with an objective of minimizing a glo-bal interconnection cost. An efficient and effective algo-rithm is necessary when the circuit is huge and the tree has many levels of hierarchy. We propose a heuristic algorithm for improving a partition with respect to a given tree struc-ture. The algorithm utilizes the tree hierarchy as an efficient mechanism for iterative improvement. We also extend the tree hierarchy to apply a multi-phase partitioning approach. Experimental results show that the algorithm significantly improves the initial partitions produced by multiway parti-tioning and by recursive partitioning. 1

Accounting for Recent Changes of Gain in Dealing with Ties in Iterative Methods for Circuit Partitioning

In iterative methods for partitioning circuits, there is often a choice among several modules which will all produce the largest available reduction in cut size if they are moved between subsets in the partition. This choice, which is usually made by popping modules off a stack, has been shown to have a considerable impact on performance. By considering the most recent change in the potential reduction in cut size associated with moving each module between subsets, the performance of this LIFO (last-in first-out) approach can be significantly improved

Replication for Logic Bipartitioning

Logic replication, the duplication of logic in order to limit communication between partitions, is an effective part of a complete partitioning solution. In this paper we seek a better understanding of the important issues in logic replication. By developing new optimizations to existing algorithms we are able to significantly improve the quality of these techniques, achieving up to 12.5 % better results than the best existing replication techniques. When integrated into our already state-of-the-art partitioner, we improve overall cutsizes by 37.8%, while requiring the duplication of at most 7 % of the logic.

Developments and experimental evaluation of partitioning algorithms for adaptive computing systems

Multi-FPGA systems offer the potential to deliver higher performance solutions than traditional computers for some low-level computing tasks. This requires a flexible hardware substrate and an automated mapping system. CHAMPION is an automated mapping system for implementing image processing applications in multi-FPGA systems under development at the University of Tennessee. CHAMPION will map applications in the Khoros Cantata graphical programming environment to hardware. The work described in this dissertation involves the automation of the CHAMPION backend design flow, which includes the partitioning problem, netlist to structural VHDL conversion, synthesis and placement and routing, and host code generation. The primary goal is to investigate the development and evaluation of three different k-way partitioning approaches. In the first and the second approaches, we discuss the development and implementation of two existing algorithms. The first approach is a hierarchical partitioning method based on topological ordering (HP). The second approach is a recursive algorithm based on the Fiduccia and Mattheyses bipartitioning heuristic (RP). We extend these algorithms to handle the multiple constraints imposed by adaptive computing systems. We also introduce a new recursive partitioning method based on topological ordering and levelization (RPL). In addition to handling the partitioning constraints, the new approach efficiently addresses the problem of minimizing the number of FPGAs used and the amount of computation, thereby overcoming some of the weaknesses of the HP and RP algorithms

Partitioning a given circuit targeting multiple Fpgas

Our approach to the problem of partitioning the design (represented as a hypergraph) into Multi-FPGAs uses a bi-level approach by initially clustering the design and then applying the bipartitioning technique iteratively. Each partition generated by the iterative bipartitioning technique should meet the constraints given by the FPGAs input-output and number of CLBs. The traditional FM partitioning can be applied to partition the circuit into multiple FPGAs. FM partitioning aims to minimize the number of interconnections but fails to group the nodes with maximum interconnections into one partition. Thus FM algorithm looks at the partitioning problem with a global viewpoint, abandoning the details. The proposed algorithm adds another level of optimization to the partitioning heuristic. By clustering the nodes that are connected very closely in a netlist before partitioning, local optimization property is added to the FM algorithm. This clustered circuit is then partitioned to implement the design in multiple FPGAs. Bipartitioning using the Fiduccia Mattheyses algorithm is applied. (Abstract shortened by UMI.)

Formula partitioning revisited

Dividing a Boolean formula into smaller independent sub-formulae can be a useful technique for accelerating the solution of Boolean problems, including SAT and #SAT. Nevertheless, and despite promising early results, formula partitioning is hardly used in state-of-the-art solvers. In this paper, we show that this is rooted in a lack of consistency of the usefulness of formula partitioning techniques. In particular, we evaluate two existing and a novel partitioning model, coupled with two existing and two novel partitioning algorithms, on a wide range of benchmark instances. Our results show that there is no one-size-fits-all solution: for different formula types, different partitioning models and algorithms are the most suitable. While these results might seem negative, they help to improve our understanding about formula partitioning; moreover, the findings also give guidance as to which method to use for what kinds of formulae