High integrity hardware-software codesign

Programmable logic devices (PLDs) are increasing in complexity and speed, and are being used as important components in safety-critical systems. Methods for developing high-integrity software for these systems are well-known, but this is not true for programmable logic. We propose a process for developing a system incorporating software and PLDs, suitable for safety critical systems of the highest levels of integrity. This process incorporates the use of Synchronous Receptive Process Theory as a semantic basis for specifying and proving properties of programs executing on PLDs, and extends the use of SPARK Ada from a programming language for safety-critical systems software to cover the interface between software and programmable logic. We have validated this approach through the specification and development of a substantial safety-critical system incorporating both software and programmable logic components, and the development of tools to support this work. This enables us to claim that the methods demonstrated are not only feasible but also scale up to realistic system sizes, allowing development of such safety-critical software-hardware systems to the levels required by current system safety standards

Applications of reprogrammability in algorithm acceleration

This doctoral thesis consists of an introductory part and eight appended publications, which deal with hardware-based reprogrammability in algorithm acceleration with a specific emphasis on the possibilities offered by modern large-scale Field Programmable Gate Arrays (FPGAs) in computationally demanding applications. The historical evolution of both the theoretical and technological paths culminating in the introduction of reprogrammable logic devices is first outlined. This is followed by defining the commonly used terms in the thesis. The reprogrammable logic market is surveyed, and the architectural structures and the technological reasonings behind them are described in detail. As reprogrammable logic lies between Application Specific Integrated Circuits (ASICs) and general-purpose microprocessors in the implementation spectrum of electronics systems, special attention has been paid to differentiate these three implementation approaches. This has been done to emphasize, that reprogrammable logic offers much more than just a low-volume replacement for ASICs. Design systems for reprogrammable logic are investigated, as the learning curve associated with them is the main hurdle for software-oriented designers for using reprogrammable logic devices. The theoretically important topic of partial reprogrammability is described in detail, but it is concluded, that the practical problems in designing viable development platforms for partially reprogrammable systems will hinder its wide-spread adoption. The main technical, design-oriented, and economic applicability factors of reprogrammable logic are laid out. The main advantages of reprogrammable logic are their suitability for fine-grained bit-level parallelizable computing with a short time-to-market and low upfront costs. It is also concluded, that the main opportunities for reprogrammable logic lie in the potential of high-level design systems, and the ever-growing ASIC design gap. On the other hand, most power-conscious mass-market portable products do not seem to offer major new market potential for reprogrammable logic. The appended publications are examined and compared to contemporaneous research at other research institutions. The conclusion is that for relatively wide classes of well-defined computation problems, reprogrammable logic offers a more efficient solution than a software-centered approach, with a much shorter production cycle than is the case with ASICs.reviewe

Modelos, métodos e ferramentas para implementação de unidades de controlo virtuais

Mestrado em Engenharia Electrónica e TelecomunicaçõesAs unidades de controlo são um dos tipos de circuitos digitais mais importantes, estando presentes numa grande diversidade de aplicações, desde simples controladores de semáforos até sistemas complexos de processamento de dados. A sua função é estabelecer a sequência de operações realizadas pelo sistema a que pertencem. Dependendo da aplicação, podem ser utilizadas isoladamente ou em conjunto com outros componentes, tais como unidades de execução, sensores e actuadores. Como um caso particular de circuitos sequenciais, são normalmente descritas por modelos orientados ao estado, dos quais a máquina de estados finitos é o exemplo mais conhecido. No entanto, com a crescente complexidade dos sistemas e consequentemente das suas unidades de controlo, este modelo deixou de ser adequado para realizar a sua especificação, uma vez que não suporta a descrição explícita de hierarquia e concorrência. Nesta dissertação são abordados alguns dos modelos e linguagens mais apropriadas para este fim, em particular a máquina de estados finitos hierárquica e/ou paralela, os esquemas de grafos hierárquicos e/ou paralelos e os Statecharts. O aparecimento na última década de dispositivos lógicos de elevada capacidade e programáveis pelo utilizador foi responsável por importantes alterações no projecto de sistemas digitais, principalmente ao nível do tempo, custo e flexibilidade de projecto. Além disso, os dispositivos programáveis dinamicamente, deram origem a uma nova classe de circuitos: os sistemas reconfiguráveis. Estes podem ser usados para construir sistemas computacionais modificáveis, pelo que permitem combinar as vantagens de uma solução programável com o elevado desempenho de uma implementação em hardware. Os sistemas reconfiguráveis podem também ser utilizados em aplicações onde a quantidade de recursos de hardware necessários para uma implementação integral seja elevada e onde nem todos os sub-sistemas sejam necessários em simultâneo, sendo portanto possível e até desejável uma implementação parcial em conjunto com a sua reconfiguração dinâmica. Neste caso, devido à analogia com os sistemas de memória virtual, os sistemas reconfiguráveis são também designados por sistemas de hardware virtual e os respectivos circuitos de controlo por unidades de controlo virtuais. Como as unidades de controlo são específicas de cada projecto e normalmente bastante irregulares, torna-se necessário o estabelecimento de algumas restrições de forma a simplificar o seu projecto e reconfiguração. Nesta dissertação é proposta uma arquitectura de unidades de controlo virtuais baseada numa estrutura predefinida, parametrizável e optimizada para o dispositivo de implementação utilizado, a FPGA XC6200 da Xilinx. Esta arquitectura em conjunto com os modelos e os dispositivos lógicos programáveis utilizados permite construir unidades de controlo complexas, flexíveis, extensíveis e reutilizáveis. O processo de síntese de unidades de controlo é também abordado, com uma atenção especial para as técnicas mais apropriadas para as FPGAs. Finalmente, para suportar a reconfiguração dinâmica dos circuitos desenvolvidos, foi construída uma biblioteca de classes em C++ e um controlador (device driver) para a placa de desenvolvimento utilizada neste trabalho.Control units are one of the most important types of digital circuits. They are used in a great variety of applications, from simple traffic light controllers to complex data processing systems. Their function is to establish the sequence of operations accomplished by the system they belong to. Depending on the application, they can be used separately or together with other components, such as execution units, sensors or actuators. Because control units are a particular kind of sequential circuits, they are usually described by state-oriented models, the finite state machine being the best known example. However, with the increasing complexity of the systems and consequently of its control units, this model is becoming less adapted to perform its specification, because it does not support the explicit description of hierarchy and concurrency. This dissertation presents some of the models and languages better suited to this purpose, in particular the hierarchical and/or parallel finite state machine, the hierarchical and/or parallel graph schemes and the Statecharts formalisms. The appearance in the last decade of high capacity user programmable logic devices was responsible for important modifications in the way digital systems are designed, mainly in terms of time, cost and design flexibility. Besides, the availability of dynamically reconfigurable devices made possible the emergence of a new class of circuits: the reconfigurable systems. They can be used to build modifiable computational systems combining the advantages of a programmable solution with the high performance of a hardware implementation. The reconfigurable systems can also be used in applications where the amount of required hardware resources for an integral implementation is too high or at least bigger than desirable and where all the subsystems are not necessary simultaneously, making possible a partial implementation in conjunction with its dynamic reconfiguration. Due to the analogy with virtual memory systems, these systems can also be called virtual hardware systems and their respective control circuits virtual control units. Because the control units are specific for each project and usually very irregular, it is necessary to impose some constraints in order to simplify their design and reconfiguration. In this dissertation an architecture for virtual control units based on a predefined, parameterizable and optimized template for a particular target device, the FPGA XC6200 from Xilinx, is proposed. However, the main ideas of this architecture can also be easily applied to other FPGA families. The use of this architecture together with the hierarchical and/or parallel models and the dynamically reconfigurable logic devices allows building complex, flexible, extensible and reusable control units. This contributes to a decrease in development time and permits system updates after the completion of the design and manufacturing cycles. The control unit synthesis process is also presented with special emphasis on the techniques better suited to FPGA implementation. Finally, to support the dynamic reconfiguration of the developed circuits, a C++ class library and a device driver for the development system used in this work were built

Preemptive Multitasking auf FPGA-Prozessoren

In dieser Arbeit wird die Umsetzung eines multitaskingfähigen Betriebssystems für FPGA-Prozessoren vorgestellt. Mit diesem Betriebssystem ist es möglich, die Resource FPGA-Prozessor durch mehrere unabhängige Anwendungen gleichzeitig zu nutzen. Der wesentliche Teil der Arbeit beschäftigt sich mit der schnellen Zustandsermittlung einer Schaltung auf dem FPGA-Baustein und zugleich mit der schnellen Zustandsrekonstruktion bei erneuter Ausführung der Schaltung auf dem FPGA-Prozessor. Basierend auf diesen grundlegenden Funktionen ist ein Betriebssystem entstanden, das sowohl effektiv als auch flexibel die Verarbeitung mehrerer unabhängiger Anwendungen auf verschiedenen FPGA-Prozessoren ermöglicht. Zur weiteren Steigerung der Leistungsfähigkeit wurde im Rahmen der Arbeit ein spezieller multitaskingunterstützender FPGA-Prozessor erstellt, der durch seinen Aufbau die Prozesswechselzeiten auf ein Minimum reduziert. Durch den neuartigen Aufbau dieses FPGA-Prozessors kann die Ausführung der Anwendungen nach neuen Modellen erfolgen, die durch parallel arbeitende Schritte den FPGA-Prozessor effektiver nutzen

Evolutionary algorithms for synthesis and optimisation of sequential logic circuits

Considerable progress has been made recently 1n the understanding of combinational logic optimization. Consequently a large number of university and industrial Electric Computing Aided Design (ECAD) programs are now available for optimal logic synthesis of combinational circuits. The progress with sequential logic synthesis and optimization, on the other hand, is considerably less mature. In recent years, evolutionary algorithms have been found to be remarkably effective way of using computers for solving difficult problems. This thesis is, in large part, a concentrated effort to apply this philosophy to the synthesis and optimization of sequential circuits. A state assignment based on the use of a Genetic Algorithm (GA) for the optimal synthesis of sequential circuits is presented. The state assignment determines the structure of the sequential circuit realizing the state machine and therefore its area and performances. The synthesis based on the GA approach produced designs with the smallest area to date. Test results on standard fmite state machine (FS:M) benchmarks show that the GA could generate state assignments, which required on average 15.44% fewer gates and 13.47% fewer literals compared with alternative techniques. Hardware evolution is performed through a succeSSlOn of changes/reconfigurations of elementary components, inter-connectivity and selection of the fittest configurations until the target functionality is reached. The thesis presents new approaches, which combine both genetic algorithm for state assignment and extrinsic Evolvable Hardware (EHW) to design sequential logic circuits. The implemented evolutionary algorithms are able to design logic circuits with size and complexity, which have not been demonstrated in published work. There are still plenty of opportunities to develop this new line of research for the synthesis, optimization and test of novel digital, analogue and mixed circuits. This should lead to a new generation of Electronic Design Automation tools.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

A Field Programmable Gate Array Architecture for Two-Dimensional Partial Reconfiguration

Reconfigurable machines can accelerate many applications by adapting to their needs through hardware reconfiguration. Partial reconfiguration allows the reconfiguration of a portion of a chip while the rest of the chip is busy working on tasks. Operating system models have been proposed for partially reconfigurable machines to handle the scheduling and placement of tasks. They are called OS4RC in this dissertation. The main goal of this research is to address some problems that come from the gap between OS4RC and existing chip architectures and the gap between OS4RC models and practical applications. Some existing OS4RC models are based on an impractical assumption that there is no data exchange channel between IP (Intellectual Property) circuits residing on a Field Programmable Gate Array (FPGA) chip and between an IP circuit and FPGA I/O pins. For models that do not have such an assumption, their inter-IP communication channels have severe drawbacks. Those channels do not work well with 2-D partial reconfiguration. They are not suitable for intensive data stream processing. And frequently they are very complicated to design and very expensive. To address these problems, a new chip architecture that can better support inter-IP and IP-I/O communication is proposed and a corresponding OS4RC kernel is then specified. The proposed FPGA architecture is based on an array of clusters of configurable logic blocks, with each cluster serving as a partial reconfiguration unit, and a mesh of segmented buses that provides inter-IP and IP-I/O communication channels. The proposed OS4RC kernel takes care of the scheduling, placement, and routing of circuits under the constraints of the proposed architecture. Features of the new architecture in turns reduce the kernel execution times and enable the runtime scheduling, placement and routing. The area cost and the configuration memory size of the new chip architecture are calculated and analyzed. And the efficiency of the OS4RC kernel is evaluated via simulation using three different task models

Evolutionary algorithms for synthesis and optimisation of sequential logic circuits.

Considerable progress has been made recently 1n the understanding ofcombinational logic optimization. Consequently a large number of universityand industrial Electric Computing Aided Design (ECAD) programs are nowavailable for optimal logic synthesis of combinational circuits. The progresswith sequential logic synthesis and optimization, on the other hand, isconsiderably less mature.In recent years, evolutionary algorithms have been found to be remarkablyeffective way of using computers for solving difficult problems. This thesis is,in large part, a concentrated effort to apply this philosophy to the synthesisand optimization of sequential circuits.A state assignment based on the use of a Genetic Algorithm (GA) for theoptimal synthesis of sequential circuits is presented. The state assignmentdetermines the structure of the sequential circuit realizing the state machineand therefore its area and performances. The synthesis based on the GAapproach produced designs with the smallest area to date. Test results onstandard fmite state machine (FS:M) benchmarks show that the GA couldgenerate state assignments, which required on average 15.44% fewer gatesand 13.47% fewer literals compared with alternative techniques.Hardware evolution is performed through a succeSSlOn ofchanges/reconfigurations of elementary components, inter-connectivity andselection of the fittest configurations until the target functionality is reached.The thesis presents new approaches, which combine both genetic algorithmfor state assignment and extrinsic Evolvable Hardware (EHW) to designsequential logic circuits. The implemented evolutionary algorithms are able todesign logic circuits with size and complexity, which have not beendemonstrated in published work.There are still plenty of opportunities to develop this new line of research forthe synthesis, optimization and test of novel digital, analogue and mixedcircuits. This should lead to a new generation of Electronic DesignAutomation tools

Coprocesadores dinámicamente reconfigurables en sistemas embebidos basados en FPGAs: Tesis doctoral

Tesis doctoral inédita leída en la Universidad Autónoma de Madrid. Escuela Politécnica Superior, Departamento de Ingeniería Informática. Fecha de lectura: 12-05-2006