144 research outputs found
Lowering the Error Floor of LDPC Codes Using Cyclic Liftings
Cyclic liftings are proposed to lower the error floor of low-density
parity-check (LDPC) codes. The liftings are designed to eliminate dominant
trapping sets of the base code by removing the short cycles which form the
trapping sets. We derive a necessary and sufficient condition for the cyclic
permutations assigned to the edges of a cycle of length in the
base graph such that the inverse image of in the lifted graph consists of
only cycles of length strictly larger than . The proposed method is
universal in the sense that it can be applied to any LDPC code over any channel
and for any iterative decoding algorithm. It also preserves important
properties of the base code such as degree distributions, encoder and decoder
structure, and in some cases, the code rate. The proposed method is applied to
both structured and random codes over the binary symmetric channel (BSC). The
error floor improves consistently by increasing the lifting degree, and the
results show significant improvements in the error floor compared to the base
code, a random code of the same degree distribution and block length, and a
random lifting of the same degree. Similar improvements are also observed when
the codes designed for the BSC are applied to the additive white Gaussian noise
(AWGN) channel
Near-capacity fixed-rate and rateless channel code constructions
Fixed-rate and rateless channel code constructions are designed for satisfying conflicting design tradeoffs, leading to codes that benefit from practical implementations, whilst offering a good bit error ratio (BER) and block error ratio (BLER) performance. More explicitly, two novel low-density parity-check code (LDPC) constructions are proposed; the first construction constitutes a family of quasi-cyclic protograph LDPC codes, which has a Vandermonde-like parity-check matrix (PCM). The second construction constitutes a specific class of protograph LDPC codes, which are termed as multilevel structured (MLS) LDPC codes. These codes possess a PCM construction that allows the coexistence of both pseudo-randomness as well as a structure requiring a reduced memory. More importantly, it is also demonstrated that these benefits accrue without any compromise in the attainable BER/BLER performance. We also present the novel concept of separating multiple users by means of user-specific channel codes, which is referred to as channel code division multiple access (CCDMA), and provide an example based on MLS LDPC codes. In particular, we circumvent the difficulty of having potentially high memory requirements, while ensuring that each user’s bits in the CCDMA system are equally protected. With regards to rateless channel coding, we propose a novel family of codes, which we refer to as reconfigurable rateless codes, that are capable of not only varying their code-rate but also to adaptively modify their encoding/decoding strategy according to the near-instantaneous channel conditions. We demonstrate that the proposed reconfigurable rateless codes are capable of shaping their own degree distribution according to the nearinstantaneous requirements imposed by the channel, but without any explicit channel knowledge at the transmitter. Additionally, a generalised transmit preprocessing aided closed-loop downlink multiple-input multiple-output (MIMO) system is presented, in which both the channel coding components as well as the linear transmit precoder exploit the knowledge of the channel state information (CSI). More explicitly, we embed a rateless code in a MIMO transmit preprocessing scheme, in order to attain near-capacity performance across a wide range of channel signal-to-ratios (SNRs), rather than only at a specific SNR. The performance of our scheme is further enhanced with the aid of a technique, referred to as pilot symbol assisted rateless (PSAR) coding, whereby a predetermined fraction of pilot bits is appropriately interspersed with the original information bits at the channel coding stage, instead of multiplexing pilots at the modulation stage, as in classic pilot symbol assisted modulation (PSAM). We subsequently demonstrate that the PSAR code-aided transmit preprocessing scheme succeeds in gleaning more information from the inserted pilots than the classic PSAM technique, because the pilot bits are not only useful for sounding the channel at the receiver but also beneficial for significantly reducing the computational complexity of the rateless channel decoder
Spatially Coupled Codes and Optical Fiber Communications: An Ideal Match?
In this paper, we highlight the class of spatially coupled codes and discuss
their applicability to long-haul and submarine optical communication systems.
We first demonstrate how to optimize irregular spatially coupled LDPC codes for
their use in optical communications with limited decoding hardware complexity
and then present simulation results with an FPGA-based decoder where we show
that very low error rates can be achieved and that conventional block-based
LDPC codes can be outperformed. In the second part of the paper, we focus on
the combination of spatially coupled LDPC codes with different demodulators and
detectors, important for future systems with adaptive modulation and for
varying channel characteristics. We demonstrate that SC codes can be employed
as universal, channel-agnostic coding schemes.Comment: Invited paper to be presented in the special session on "Signal
Processing, Coding, and Information Theory for Optical Communications" at
IEEE SPAWC 201
A New Class of Multiple-rate Codes Based on Block Markov Superposition Transmission
Hadamard transform~(HT) as over the binary field provides a natural way to
implement multiple-rate codes~(referred to as {\em HT-coset codes}), where the
code length is fixed but the code dimension can be varied from
to by adjusting the set of frozen bits. The HT-coset codes, including
Reed-Muller~(RM) codes and polar codes as typical examples, can share a pair of
encoder and decoder with implementation complexity of order .
However, to guarantee that all codes with designated rates perform well,
HT-coset coding usually requires a sufficiently large code length, which in
turn causes difficulties in the determination of which bits are better for
being frozen. In this paper, we propose to transmit short HT-coset codes in the
so-called block Markov superposition transmission~(BMST) manner. At the
transmitter, signals are spatially coupled via superposition, resulting in long
codes. At the receiver, these coupled signals are recovered by a sliding-window
iterative soft successive cancellation decoding algorithm. Most importantly,
the performance around or below the bit-error-rate~(BER) of can be
predicted by a simple genie-aided lower bound. Both these bounds and simulation
results show that the BMST of short HT-coset codes performs well~(within one dB
away from the corresponding Shannon limits) in a wide range of code rates
An efficient reconfigurable code rate cooperative low-density parity check codes for gigabits wide code encoder/decoder operations
In recent days, extensive digital communication process has been performed. Due to this phenomenon, a proper maintenance of authentication, communication without any overhead such as signal attenuation code rate fluctuations during digital communication process can be minimized and optimized by adopting parallel encoder and decoder operations. To overcome the above-mentioned drawbacks by using proposed reconfigurable code rate cooperative (RCRC) and low-density parity check (LDPC) method. The proposed RCRC-LDPC is capable to operate over gigabits/sec data and it effectively performs linear encoding, dual diagonal form, widens the range of code rate and optimal degree distribution of LDPC mother code. The proposed method optimize the transmission rate and it is capable to operate on 0.98 code rate. It is the highest upper bounded code rate as compared to the existing methods. The proposed method optimizes the transmission rate and is capable to operate on a 0.98 code rate. It is the highest upper bounded code rate as compared to the existing methods. the proposed method's implementation has been carried out using MATLAB and as per the simulation result, the proposed method is capable of reaching a throughput efficiency greater than 8.2 (1.9) gigabits per second with a clock frequency of 160 MHz
Challenges and Some New Directions in Channel Coding
Three areas of ongoing research in channel coding are surveyed, and recent developments are presented in each area: spatially coupled Low-Density Parity-Check (LDPC) codes, nonbinary LDPC codes, and polar coding.This is the author accepted manuscript. The final version is available from IEEE via http://dx.doi.org/10.1109/JCN.2015.00006
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