The modified Max-Log-MAP turbo decoding algorithm by extrinsic information scaling for wireless applications

The iterative nature of turbo-decoding algorithms increases their complexity compare to conventional FEC decoding algorithms. Two iterative decoding algorithms, Soft-Output-Viterbi Algorithm (SOVA) and Maximum A posteriori Probability (MAP) Algorithm require complex decoding operations over several iteration cycles. So, for real-time implementation of turbo codes, reducing the decoder complexity while preserving bit-error-rate (BER) performance is an important design consideration. In this chapter, a modification to the Max-Log-MAP algorithm is presented. This modification is to scale the extrinsic information exchange between the constituent decoders. The remainder of this chapter is organized as follows: An overview of the turbo encoding and decoding processes, the MAP algorithm and its simplified versions the Log-MAP and Max-Log-MAP algorithms are presented in section 1. The extrinsic information scaling is introduced, simulation results are presented, and the performance of different methods to choose the best scaling factor is discussed in Section 2. Section 3 discusses trends and applications of turbo coding from the perspective of wireless applications

On chip interconnects for multiprocessor turbo decoding architectures

International audienc

Further Specialization of Clustered VLIW Processors: A MAP Decoder for Software Defined Radio

Turbo codes are extensively used in current communications standards and have a promising outlook for future generations. The advantages of software defined radio, especially dynamic reconfiguration, make it very attractive in this multi-standard scenario. However, the complex and power consuming implementation of the maximum a posteriori (MAP) algorithm, employed by turbo decoders, sets hurdles to this goal. This work introduces an ASIP architecture for the MAP algorithm, based on a dual-clustered VLIW processor. It displays the good performance of application specific designs along with the versatility of processors, which makes it compliant with leading edge standards. The machine deals with multi-operand instructions in an innovative way, the fetching and assertion of data is serialized and the addressing is automatized and transparent for the programmer. The performance-area trade-off of the proposed architecture achieves a throughput of 8 cycles per symbol with very low power dissipation

The IST project MATRICE on MC-CDMA transmission techniques for future Cellular Systems

This paper presents an overview of the European IST project MATRICE (MC-CDMA Transmission Techniques for Integrated Broadband Cellular Systems, IST-2001-3220), describing its tasks, goals and preliminary achievements. The main focus of the MATRICE project is the definition of a new air-interface for future cellular mobile radio systems based on Multicarrier-CDMA modulation techniques and the study of its key building blocks like receiver algorithms and flexible TX components. The nine European partners participating in this project are CEA-LETI (F), France Telecom (F), Instituto de Telecommonicaçõ (P), Mitsubishi Electric ITE-TCL (F), University of Madrid (E), University of Surrey (UK), STMicroelectronics (CH), INSA-IETR (F) and Nokia (D)

IST-2000-30148 I-METRA: D3.1 Design, analysis and selection of suitable algorithms

This deliverable contains a description of the space-time coding algorithms to be simulated within the I-METRA project. Different families of algorithms have been selected and described in this document with the objective of evaluating their performance. One of the main objectives of the I-METRA project is to impact into the current standardisation efforts related to the introduction of Multiple Input Multiple Output (MIMO) configurations into the High Speed Downlink and Uplink Packet Access concepts of UMTS (HSDPA and HSUPA). This required a review of the current specifications for these systems and the analysis of the impact of the potential incorporation of the selected MIMO schemes.Preprin

Smart antennas: state of the art

Aim of this contribution is to illustrate the state of the art of smart antenna research from several perspectives. The bow is drawn from transmitter issues via channel measurements and modeling, receiver signal processing, network aspects, technological challenges towards first smart antenna applications and current status of standardization. Moreover, some future prospects of different disciplines in smart antenna research are given.Peer Reviewe

Improved decoder metrics for DS-CDMA in practical 3G systems

While 4G mobile networks have been deployed since 2008. In several of the more developed markets, 3G mobile networks are still growing with 3G having the largest market -in terms of number of users- by 2019. 3G networks are based on Direct- Sequence Code-Division Multiple-Access (DS-CDMA). DS-CDMA suffers mainly from the Multiple Access Interference (MAI) and fading. Multi-User Detectors (MUDs) and Error Correcting Codes (ECCs) are the primary means to combat MAI and fading. MUDs, however, suffer from high complexity, including most of sub-optimal algorithms. Hence, most commercial implementations still use conventional single-user matched filter detectors. This thesis proposes improved channel decoder metrics for enhancing uplink performance in 3G systems. The basic idea is to model the MAI as conditionally Gaussian, instead of Gaussian, conditioned on the users’ cross-correlations and/or the channel fading coefficients. The conditioning implies a time-dependent variance that provides enhanced reliability estimates at the decoder inputs. We derive improved log-likelihood ratios (ILLRs) for bit- and chip- asynchronous multipath fading channels. We show that while utilizing knowledge of all users’ code sequences for the ILLR metric is very complicated in chip-asynchronous reception, a simplified expression relying on truncated group delay results in negligible performance loss. We also derive an expression for the error probability using the standard Gaussian approximation for asynchronous channels for the widely used raised cosine pule shaping. Our study framework considers practical 3G systems, with finite interleaving, correlated multipath fading channel models, practical pulse shaping, and system parameters obtained from CDMA2000 standard. Our results show that for the fully practical cellular uplink channel, the performance advantage due to ILLRs is significant and approaches 3 dB

A New Simplified Algorithm Suitable for Implementation on FPGA for Turbo Codes

In this thesis, a new algorithm for Turbo codes and a novel implementation of turbo decoder employed with this algorithm is developed. The decoder has an optimal performance in terms of Bit Error Rate(BER) in all Signal to Noise Ratio(SNR) for all frame sizes and any states of Turbo codes. In hardware implementation, we combine the normalization and matrices modules in a single module in order to minimize the internal connection delay which is the bottleneck in hardware implementation, so that the result can be obtained in one single clock signal. Having implemented in this fashion, data rate of 28Mbps for16 state decoder has been achieved. This can be further improved by changing the algorithm for the normalization modules and LLR modules with MAX operator. The matrices modules with the proposed algorithm and the normalization and LLR modules with MAX-LOG-MAP algorithm have been implemented to achieve a data rate of 60Mbps