Torque Control

This book is the result of inspirations and contributions from many researchers, a collection of 9 works, which are, in majority, focalised around the Direct Torque Control and may be comprised of three sections: different techniques for the control of asynchronous motors and double feed or double star induction machines, oriented approach of recent developments relating to the control of the Permanent Magnet Synchronous Motors, and special controller design and torque control of switched reluctance machine

Front End of a 900MHz RFID for Biological Sensing

This thesis presents the front end of a 900MHz passive RFID for biological sensing. The components blocks of the front end consist of power harvester, switch capacitor voltage regulator, phase lock loop and a modulator and demodulator. As the RFID is passive so the power resource is limited hence the main focus while implementing all the block was low power and high efficiency power conversion. All the individual block were optimized to provide maximum efficiency. For the harvester to achieve high efficiency and high output voltage a design approach is discussed by which the device sizes are optimized and the values of the matching network components are solved. The efficiency achieved with this approach is 34% while supplying 74�[email protected]. The switch capacitor voltage regulator would supply power to the digital core of the RFID, which will operate at subtheshold or moderate inversion. The switch capacitor implemented in this work is a adaptive voltage regulator, as I intend to use the dynamic supply voltage scaling technique to compensate for the reduction in reliability of performance of the circuit due to variation of VTH across process due to random doping effects and temperature in subthreshold.The phase lock loop (PLL) block in this front end provide the system clock synchronized with the base station to all the backend blocks like the digital controller, memory, and the analog to digital converter ADC and the switch capacitor voltage regulator. The PLL is a low power with jitter of 24nsec and is capable of clock data recovery from EPC gen 2 protocol format data and consumes 3�W of power Finally a ultra low power AM (amplitude modulation) demodulator is presented which is consumes only 100nW and is capable of demodulating a double-sideband amplitude modulated (DSB-AM) signal centered at 900MHz and the modulating frequency is 160KHz. The demodulator can demodulate signal having as low as -5dBm power and 50% modulation index. The modulation for transmitting signal is achieved by BPSK(back scatter phase shift keying).Electrical Engineerin

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

Development of new parameter extraction schemes and maximum power point controllers for photovoltaic power systems

In the recent years, in every parts of the world, focus is on supplementing the conventional fossil fuel based power generation with power generated from renewable sources such as photovoltaic (PV) and wind systems. PV technology is one of the fastest growing energy technologies in the world owing to its abundant availability. But unfortunately, the cost of PV energy is higher than that of other electrical energy from other conventional sources.Therefore, a great deal of research opportunities lie in applying power electronics and control technologies for harvesting PV power at higher efficiencies and efficient utilization. Simulation and control studies of a PV system require an accurate PV panel model. Further, for efficient utilization of the available PV energy, a PV system should operate at its maximum power point (MPP). A maximum power point tracker (MPPT) is needed in the PV system to enable it to operate at the MPP.The output characteristic of a PV system is non-linear and its output power fluctuates to a large extent in accordance with the variation of solar irradiance and temperature. A lot of research is being pursued on this area and several MPPT techniques have been proposed and implemented. But, still there is a lot of scope on designing new parameter extraction algorithms to achieve fast and accurate extraction of PV panel parameters. Further, there is need of development of efficient MPPT algorithms that can be adapted to different weather conditions with minimal fluctuations in input PV current and voltage.The work described in the thesis involves development of some new parameter extraction and robust adaptive MPPT algorithms. Two parameter extraction algorithms have been proposed namely a hybrid Newton Raphson method (hybrid NRM) and an evolutionary computational technique called Bacterial Foraging Optimization (BFO). These two parameter extraction techniques are found to be extracting parameters of a PV panel accurately in all weather conditions with less computational overhead. Further, these two parameter extraction techniques do not suffer from singularity problem during convergence. BFO technique being a global optimization technique provides accurate PV panel parameters

The 1991 3rd NASA Symposium on VLSI Design

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2

Development of a New Rapid Screening Method for High Throughput Electrochemical Characterization of NiMo Hydrogen Evolution Catalysts

In order to effectively study new electrocatalysts for hydrogen evolution (using water as a renewable and clean feedstock) new advancements must be made with the analytic techniques used to characterize these electrocatalysts. In this thesis, two new methods are presented for measuring heterogeneous electrocatalyst electron transfer kinetics. The first of these methods is intended to advance the capabilities of high throughput rapid screening methods for electrocatalysts. By using piezoelectric printing, precursors for metal and metal oxide catalysts are printed onto a substrate, yielding arrays of 64 catalyst samples to be analyzed by linear sweep voltammetry (LSV). Combining piezoelectric printing technologies with automated process controls (used to control the electrochemical reaction systems) and automated high throughput COMSOL Multiphysics simulations allows for the number of catalyst samples that can be measured in one set are increased exponentially compared to other methods capable of returning kinetic parameter data (k0eff) without sample crosstalk. To verify the capabilities of this method, 2% incremental composition NiMo bimetallic hydrogen evolution catalyst arrays (from 100% Ni to 100% Mo) were studied in both acidic and neutral pH electrolyte solutions, yielding catalytic reactivity maps of the composition arrays. For the acidic reaction conditions, peak activity of the NiMo catalyst occurred in the composition range of 78-90% Ni, whereas for the neutral reaction conditions, peak activity regions occurred at 12-18% Ni and 46-62% Ni. The second method of measuring kinetics of electron transfer reactions is an improved controls system for Scanning Electrochemical Microscopy (SECM) motion control. To improve the efficiency of the SECM approach for electrodes, a new variable approach speed technique was developed to employ custom fuzzy logic control algorithms for automatically adjusting the speed of approach for the electrode based on tip size, detection method, enhancement factor, and distance of the electrode tip from the set-point. This algorithm is able to automatically switch from a coarse to a fine motion controller when the tip electrode is sufficiently close to the substrate. We validated that approach curves obtained using the fuzzy logic algorithm matched well with simulated approach curves for both large microelectrodes (d = 175 μm) and for conventional SECM ultramicroelectrodes (d = 6.2 μm and d = 4.2 μm). Using positive feedback approach curves, we obtained a tip/substrate gap distance of 6.5 μm for the 175 μm electrode, 800 nm for the 6.2 μm electrode, and 580 nm for the 4.2 μm electrode. The gap distances were obtained using the fuzzy logic control algorithm in roughly one-third of the time compared to the conventional constant-speed approach method. Also, the gap distances were closer using the fuzzy logic algorithm, with the 4.2 μm electrode gap being 120 nm smaller than the constant-speed approach method. In addition, at the 580 nm gap distance obtained with the fuzzy logic algorithm, linear sweep voltammetry was performed allowing us to quantify the kinetic rate constant (k0) for the oxidation reaction of ferrocenemethanol to be 0.20 ± 0.05 cm s-1

Volume 1 – Symposium: Tuesday, March 8

Group A: Digital Hydraulics Group B: Intelligent Control Group C: Valves Group D | G | K: Fundamentals Group E | H | L: Mobile Hydraulics Group F | I: Pumps Group M: Hydraulic Components:Group A: Digital Hydraulics Group B: Intelligent Control Group C: Valves Group D | G | K: Fundamentals Group E | H | L: Mobile Hydraulics Group F | I: Pumps Group M: Hydraulic Component

Design and test of digitally-controlled power management IPs in advanced CMOS technologies

Les technologies avancées de semi-conducteur permettent de mettre en œuvre un contrôleur numérique dédié aux convertisseurs à découpage, de faible puissance et de fréquence de découpage élevée sur FPGA et ASIC. Cette thèse vise à proposer des contrôleurs numériques des performances élevées, de faible consommation énergétique et qui peuvent être implémentés facilement. En plus des contrôleurs numériques existants comme PID, RST, tri-mode et par mode de glissement, un nouveau contrôleur numérique (DDP) pour le convertisseur abaisseur de tension est proposé sur le principe de la commande prédictive: il introduit une nouvelle variable de contrôle qui est la position de la largeur d'impulsion permettant de contrôler de façon simultanée le courant dans l'inductance et la tension de sortie. La solution permet une dynamique très rapide en transitoire, aussi bien pour la variation de la charge que pour les changements de tension de référence. Les résultats expérimentaux sur FPGA vérifient les performances de ce contrôleur jusqu'à la fréquence de découpage de 4MHz. Un contrôleur numérique nécessite une modulation numérique de largeur d'impulsion (DPWM). L'approche Sigma-Delta de la DPWM est un bon candidat en ce qui concerne le compromis entre la complexité et les performances. Un guide de conception d'étage Sigma-Delta pour le DPWM est présenté. Une architecture améliorée de traditionnelles 1-1 MASH Sigma-Delta DPWM est synthétisée sans détérioration de la stabilité en boucle fermée ainsi qu'en préservant un coût raisonnable en ressources matérielles. Les résultats expérimentaux sur FPGA vérifient les performances des DPWM proposées en régimes stationnaire et transitoire. Deux ASICs sont portés en CMOS 0,35 m: le contrôleur en tri-mode pour le convertisseur abaisseur de tension et la commande par mode de glissement pour les convertisseurs abaisseur et élévateur de tension. Les bancs de test sont conçus pour conduire à un modèle d'évaluation de consommation énergétique. Pour le contrôleur en tri-mode, la consommation de puissance mesurée est seulement de 24,56mW/MHz lorsque le ratio de temps en régime de repos (stand-by) est 0,7. Les consommations de puissance de command par mode de glissement pour les convertisseurs abaisseur et élévateur de tension sont respectivement de 4,46mW/MHz et 4,79mW/MHz. En utilisant le modèle de puissance, une consommation de la puissance estimée inférieure à 1mW/MHz est envisageable dans des technologies CMOS plus avancées. Comparé aux contrôlés homologues analogiques de l'état de l'art, les prototypes ASICs illustrent la possibilité d'atteindre un rendement comparable pour les applications de faible et de moyen puissance mais avec l'avantage d'une meilleure précision et une meilleure flexibilité.Owing to the development of modern semiconductor technology, it is possible to implement a digital controller for low-power high switching frequency DC-DC power converter in FPGA and ASIC. This thesis is intended to propose digital controllers with high performance, low power consumption and simple implementation architecture. Besides existing digital control-laws, such as PID, RST, tri-mode and sliding-mode (SM), a novel digital control-law, direct control with dual-state-variable prediction (DDP control), for the buck converter is proposed based on the principle of predictive control. Compared to traditional current-mode predictive control, the predictions of the inductor current and the output voltage are performed at the same time by adding a control variable to the DPWM signal. DDP control exhibits very high dynamic transient performances under both load variations and reference changes. Experimental results in FPGA verify the performances at switching frequency up to 4MHz. For the boost converter exhibiting more serious nonlinearity, linear PID and nonlinear SM controllers are designed and implemented in FPGA to verify the performances. A digital control requires a DPWM. Sigma-Delta DPWM is therefore a good candidate regarding the implementation complexity and performances. An idle-tone free condition for Sigma-Delta DPWM is considered to reduce the inherent tone-noise under DC-excitation compared to the classic approach. A guideline for Sigma-Delta DPWM helps to satisfy proposed condition. In addition, an 1-1 MASH Sigma-Delta DPWM with a feasible dither generation module is proposed to further restrain the idle-tone effect without deteriorating the closed-loop stability as well as to preserve a reasonable cost in hardware resources. The FPGA-based experimental results verify the performances of proposed DPWM in steady-state and transient-state. Two ASICs in 0.35 m CMOS process are implemented including the tri-mode controller for buck converter and the PID and SM controllers for the buck and boost converters respectively. The lab-scale tests are designed to lead to a power assessment model suggesting feasible applications. For the tri-mode controller, the measured power consumption is only 24.56mW/MHz when the time ratio of stand-by operation mode is 0.7. As specific power optimization strategies in RTL and system-level are applied to the latter chip, the measured power consumptions of the SM controllers for buck converter and boost converter are 4.46mW/MHz and 4.79mW/MHz respectively. The power consumption is foreseen as less than 1mW/MHz when the process scales down to nanometer technologies based on the power-scaling model. Compared to the state-of-the-art analog counterpart, the prototype ICs are proven to achieve comparable or even higher power efficiency for low-to-medium power applications with the benefit of better accuracy and better flexibility.VILLEURBANNE-DOC'INSA-Bib. elec. (692669901) / SudocSudocFranceF