Skalabilna implementacija dekodera po normi MPEG korištenjem tokovnog programskog jezika

In this paper, we describe a scalable and portable parallelized implementation of a MPEG decoder using a streaming computation paradigm, tailored to new generations of multi--core systems. A novel, hybrid approach towards parallelization of both new and legacy applications is described, where only data--intensive and performance--critical parts are implemented in the streaming domain. An architecture--independent \u27StreamIt\u27 language is used for design, optimization and implementation of parallelized segments, while the developed \u27StreamGate\u27 interface provides a communication mechanism between the implementation domains. The proposed hybrid approach was employed in re--factoring of a reference MPEG video decoder implementation; identifying the most performance--critical segments and re-implementing them in \u27StreamIt\u27 language, with \u27StreamGate\u27 interface as a communication mechanism between the host and streaming kernel. We evaluated the scalability of the decoder with respect to the number of cores, video frame formats, sizes and decomposition. Decoder performance was examined in the presence of different processor load configurations and with respect to the number of simultaneously processed frames.U ovom radu opisujemo skalabilnu i prenosivu implementaciju dekodera po normi MPEG ostvarenu korištenjem paradigme tokovnog računarstva, prilagođenu novim generacijama višejezgrenih računala. Opisan je novi, hibridni pristup paralelizaciji novih ili postojećih aplikacija, gdje se samo podatkovno intenzivni i računski zahtjevni dijelovi implementiraju u tokovnoj domeni. Arhitekturno neovisni jezik StreamIt koristi se za oblikovanje, optimiranje i izvedbu paraleliziranih segmenata aplikacije, dok razvijeno sučelje \u27StreamGate\u27 omogućava komunikaciju između domena implementacije. Predloženi hibridni pristup razvoju paraleliziranih aplikacija iskorišten je u preoblikovanju referentnog dekodera video zapisa po normi MPEG; identificirani su računski zahtjevni segmenti aplikacije i ponovno implementirani u jeziku StreamIt, sa sučeljem \u27StreamGate\u27 kao poveznicom između slijedne i tokovne domene. Ispitivana su svojstva skalabilnosti s obzirom na ciljani broj jezgri, format video zapisa i veličinu okvira te dekompoziciju ulaznih podataka. Svojstva dekodera  su praćena u prisustvu različitih opterećenja ispitnog računala, i s obzirom na broj istovremeno obrađivanih okvira

Color space adaptation for video coding

Processament d'imatges abans de ser codificades pel codificador HEVC amb la finalitat d'augmentar la qualitat i la fidelitat.[ANGLÈS] Project on the objective and subjective improvements by pre-processing images to be encoded into a video.[CASTELLÀ] Proyecto sobre la repercusión en la mejora de calidad objetiva y subjetiva del pre-procesado de imágenes a codificar con vídeo.[CATALÀ] Projecte sobre la repercussió en la millora de la qualitat objectiva i subjectiva del pre-processament d'imatges a codificar amb vídeo

A general framework for efficient FPGA implementation of matrix product

Original article can be found at: http://www.medjcn.com/ Copyright Softmotor LimitedHigh performance systems are required by the developers for fast processing of computationally intensive applications. Reconfigurable hardware devices in the form of Filed-Programmable Gate Arrays (FPGAs) have been proposed as viable system building blocks in the construction of high performance systems at an economical price. Given the importance and the use of matrix algorithms in scientific computing applications, they seem ideal candidates to harness and exploit the advantages offered by FPGAs. In this paper, a system for matrix algorithm cores generation is described. The system provides a catalog of efficient user-customizable cores, designed for FPGA implementation, ranging in three different matrix algorithm categories: (i) matrix operations, (ii) matrix transforms and (iii) matrix decomposition. The generated core can be either a general purpose or a specific application core. The methodology used in the design and implementation of two specific image processing application cores is presented. The first core is a fully pipelined matrix multiplier for colour space conversion based on distributed arithmetic principles while the second one is a parallel floating-point matrix multiplier designed for 3D affine transformations.Peer reviewe

A network transparent, retained mode multimedia processing framework for the Linux operating system environment

Die Arbeit präsentiert ein Multimedia-Framework für Linux, das im Unterschied zu früheren Arbeiten auf den Ideen "retained-mode processing" und "lazy evaluation" basiert: Statt Transformationen unmittelbar auszuführen, wird eine abstrakte Repräsentation aller Medienelemente aufgebaut. "renderer"-Treiber fungieren als Übersetzer, die diese Darstellung zur Laufzeit in konkrete Operationen umsetzen, wobei das Datenmodell zahlreiche Optimierungen zur Reduktion der Anzahl der Schritte oder der Minimierung von Kommunikation erlaubt. Dies erlaubt ein stark vereinfachtes Programmiermodell bei gleichzeitiger Effizienzsteigerung. "renderer"-Treiber können zur Ausführung von Transformationen den lokalen Prozessor verwenden, oder können die Operationen delegieren. In der Arbeit wird eine Erweiterung des X Window Systems um Mechanismen zur Medienverarbeitung vorgestellt, sowie ein "renderer"-Treiber, der diese zur Delegation der Verarbeitung nutzt

Recent advances in the hardware architecture of flat display devices

Thesis (Master)--Izmir Institute of Technology, Electronics and Communication Engineering, Izmir, 2007Includes bibliographical References (leaves: 115-117)Text in English; Abstract: Turkish and Englishxiii, 133 leavesThesis will describe processing board hardware design for flat panel displays with integrated digital reception, the design challenges in flat panel displays with integrated digital reception explained with details. Thesis also includes brief explanation of flat panel technology and processing blocks. Explanations of building blocks of TV and flat panel displays are given before design stage for better understanding of design stage. Hardware design stage of processing board is investigated in two major steps, schematic design and layout design. First step of the schematic design is system level block diagram design. Schematic diagram is the detailed application level hardware design and layout is the implementation level of the design. System level, application level and implementation level hardware design of the TV processing board is described with details in thesis. Design challenges, considerations and solutions are defined in advance for flat panel displays

Adaptive filtering of MPEG system streams in IP networks

Congestion and large differences in available link bandwidth create challenges for the design of applications that want to deliver high quality video over the Internet. We present an efficient adaptive filter for MPEG System streams that can be placed in the network (e.g., as an active service). This filter adjusts the bandwidth demands of an MPEG System stream to the available bandwidth without transcoding while maintaining synchronization between the streams embedded in the MPEG System. The filter is network-friendly: it is fair with respect to other (TCP) competing streams and it avoids generating bursty traffic. This paper presents the system architecture and an evaluation of our implementation in three different operating environments: a networking testbed in a laboratory environment, a home-user scenario (DSL line with 640Kbit/s), and a wide area network covering the Atlantic (server in Europe, client in the US). Moreover we examine the network-friendliness of the adaptation protocol and the relationship between the quality of the received continuous media and the protocol's aggressiveness. Our architecture is based on efficient MPEG System filtering to achieve high-quality video over best-effort network

Platforms for handling and development of audiovisual data

Estágio realizado na MOG Solutions e orientado por Vítor TeixeiraTese de mestrado integrado. Engenharia Informátca e Computação. Faculdade de Engenharia. Universidade do Porto. 200

An Efficient Method to Improve the Audio Quality Using AAC Low Complexity Decoder

This paper presents a new approach to design a Digital Audio Broadcast (DAB) audio decoder is introduced to improve the superiority of audio. Countries all over the world use DAB broadcasting systems more prominently, in Europe. DAB+ is the upgraded version of digital audio broadcasting. DAB and DAB+ coexist in many countries, so receivers are essential to be compatible with both standards. DAB+ is approximately twice as efficient as DAB due to the adoption of the AAC+ audio codec, and DAB+ can provide high quality audio with bit rates as low as 64 kbit/s. Integrating an MPEG-1 Layer II (MP2) decoder and Advanced Audio Coding Low Complexity (AAC LC) decoder provides a fundamental audio decoding for DAB and DAB+. The generated audio frames data from the DAB channel decoders are stored in RAM. The bit stream demultiplexer parses the quantized spectrum data in the audio. The inverse quantization performs the inverse quantization computation and synthesis filter generates the time domain Pulse Code Modulation (PCM) samples, all the above operation results writes them back to the audio RAM. The existing system of this project uses HE AAC V2 decoder, that system consists has SBR and PS technologies. This two technologies are used to improve the sound quality in low bit rate program. The proposed scheme is uses AAC LC and MP2 decoder it improve the sound quality in high bit rate. The simulation of this project is carried out by using MATLAB R2011a and Xilinx ISE 9.2i. DOI: 10.17762/ijritcc2321-8169.15039