A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI

This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC-DC switches, DC-DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices

Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies

CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections

Design of a low-voltage CMOS RF receiver for energy harvesting sensor node

In this thesis a CMOS low-power and low-voltage RF receiver front-end is presented. The main objective is to design this RF receiver so that it can be powered by a piezoelectric energy harvesting power source, included in a Wireless Sensor Node application. For this type of applications the major requirements are: the low-power and low-voltage operation, the reduced area and cost and the simplicity of the architecture. The system key blocks are the LNA and the mixer, which are studied and optimized with greater detail, achieving a good linearity, a wideband operation and a reduced introduction of noise. A wideband balun LNA with noise and distortion cancelling is designed to work at a 0.6 V supply voltage, in conjunction with a double-balanced passive mixer and subsequent TIA block. The passive mixer operates in current mode, allowing a minimal introduction of voltage noise and a good linearity. The receiver analog front-end has a total voltage conversion gain of 31.5 dB, a 0.1 - 4.3 GHz bandwidth, an IIP3 value of -1.35 dBm, and a noise figure lower than 9 dB. The total power consumption is 1.9 mW and the die area is 305x134.5 m2, using a standard 130 nm CMOS technology

Addressing On-Chip Power Conversion and Dissipation Issues in Many-Core System-on-a-Chip based on Conventional Silicon and Emerging Nanotechnologies

Title from PDF of title page viewed August 27, 2018Dissertation advisor: Masud H ChowdhuryVitaIncludes bibliographical references (pages 158-163)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2017Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon-on ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability to control the threshold voltage via bias voltage at the back gate makes both devices more flexible for sleep transistors design than a bulk MOSFET. The proposed approaches simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep transistor, and improve power dissipation. In addition, the design provides a dynamically controlled Vt for times when the circuit needs to be in a sleep or switching mode.Introduction -- Background and literature review -- Fully integrated on-chip switching voltage regulator -- Hybrid LDO voltage regulator based on cascaded second order multiple feedback loop -- Single and dual output two-stage on-chip power management system -- Sleep transistor design using double-gate FDSOI -- Subthreshold region sleep transistor design -- Conclusio

Single-phase inverter with active ripple energy storage

It is well known that conventional energy sources such as coal, oil, and natural gas are decreasing and a growing problem of environmental pollution. The renewable energy sources are becoming the best alternative for a clean and inexhaustible energy source, and solar energy is one of the most popular energy sources. Solar energy has gained more and more attention because of its advantages such as abundance, pollution free, renewability and low maintenance. The solar energy is usually obtained from photovoltaic (PV) cell which transform the solar irradiance into direct current (DC), that is electric energy. Since the majority of the electric devices and the main grid, require AC (alternate current) a power converter is needed to convert the DC electricity coming from the PV cell into AC electricity. The most used electronic converter for that is an inverter. Inverters contains semiconductor switches that are often controlled using the pulse width modulation technique, which yields second-order harmonic currents and corresponding ripple voltages on the DC bus. This double line frequency on the DC bus affect the performance of the photovoltaic system. Bulky DC link electrolytic capacitors are typically employed as transient energy buffer to decouple, or smooth out, the pulsating ac power from constant dc power. However, the use of electrolytic capacitor leads to temperature and aging concerns, and this also result in a low power density. A novel active power decoupling method proposed to add a bidirectional buck and boost converter that can store the ripple energy in its inductor and capacitor. This method can effectively reduce the energy storage in the DC link capacitor. This thesis deals with the design of such as bidirectional DC-DC converter and an inverter. The theoretical work mode of the bidirectional converter together with an inverter is studied. The power stages, inverter and bidirectional converter are studied in steady state to dimension the components. These stages are also modelled in their small signal equivalent model to find their transfer functions need to design the control loops. Different control strategies are studied and implemented to achieve the independent controls of the inverter and DC-DC converter. By using LTspice, the simulation results have verified the proposed power decoupling method.Es bien conocido que las fuentes de energía convencionales como el carbón, petróleo y gas natural están disminuyendo y volviéndose un problema de contaminación ambiental. Las fuentes de energías renovables están llegando a ser la mejor alternativa para a una fuente de energía limpia e inagotable y la energía solar es una de la más popular fuente de energía. La energía solar ha ganado más y más atención por sus ventajas, tales como, abundancia, libre de polución, renovabilidad y poco mantenimiento. La energía solar es normalmente obtenida de una célula fotovoltaica (FV) la cual transforma la irradiancia solar en corriente continua (CC), es decir, en energía eléctrica. Como la mayoría de los dispositivos electrónicos y la red requieren corriente alterna (CA) un convertidor de potencia es necesitado para convertir la electricidad continua proveniente de la célula fotovoltaica en electricidad alterna. El dispositivo más usado para esto es un inversor. Los inversores contienen conmutadores semiconductores que son a menudo controlados usando la técnica de modulación por ancho de pulso la cual produce un armónico de segundo orden en la corriente que da a lugar un rizado en el voltaje del bus de continua. Esta frecuencia de dos veces la frecuencia de línea en el bus de continua afecta el rendimiento del sistema fotovoltaico. Grandes condensadores electrolíticos son típicamente usados como buffer de energía transitoria para desacoplar, o suavizar, la potencia alterna de la potencia continua. Sin embargo, el uso de condensadores electrolíticos da lugar a problemas de temperatura y degeneración y estos además resultan en una baja densidad de potencia. Un método novedoso propone añadir un convertidor elevador reductor, bidireccional, que almacene la energía de rizado en sus inductor y capacitor. Este método puede reducir eficazmente la energía almacenada en el condensador usado en el DC link. Esta tesis trata sobre el diseño de un convertidor CC-CC bidireccional y un inversor. El modo de operación teórico del convertidor bidireccional junto con un inversor es estudiado. Las etapas de potencia, inversor y convertidor bidireccional son estudiadas en estado estacionario para dimensionar los componentes. Estas etapas son también modeladas en su modelo equivalente en pequeña señal para encontrar sus funciones de transferencia necesarias para el diseño de los lazos de control. Diferentes estrategias de control son estudiadas e implementadas para conseguir el control del inversor y del convertidor de continua. Usando LTspice, los resultados de las simulaciones han verificado el método propuesto de desacoplo de potencia.Sutil Ortiz, AM. (2018). Inversor monofásico con corrección activa de rizado. Universitat Politècnica de València. http://hdl.handle.net/10251/103423TFG

Multilevel multistate hybrid voltage regulator

In this work, a new set of voltage regulators as well as some controlling methods and schemes are proposed. While normal switched capacitor voltage regulators are easy integrable, they are suffering from charge sharing losses as well as fast degradation of efficiency when deviating from target operation point. On the other hand, conventional buck converters use bulky magnetic components that introduce challenges to integrate them on chip. The new set of voltage regulators covers the gap between inductor-based and capacitor-based voltage regulators by taking the advantages of both of them while avoiding or minimizing their disadvantages. The voltage regulator device consists of a switched capacitor circuit that is periodically switching its output between different voltage levels followed by a low pass filter to give a regulated output voltage. The voltage regulator is capable of converting an input voltage to a wide range of output voltage with a high efficiency that is roughly constant over the whole operation range. By switching between adjacent voltage levels, the voltage drop on the inductor is limited allowing for the use of smaller inductor sizes while maintaining the same performance. The general concept of the proposed voltage regulator as well as some operating conditions and techniques are explained. A phase interleaving technique to operate the multilevel multistate voltage regulator has been proposed. In this technique, the phases of two or more voltage levels are interleaved which enhances the effective switching frequency of the charge transferring components. This results in a further boost in the proposed regulator\u27s performance. A 4-level 4-state hybrid voltage regulator has been introduced as an application on the proposed concepts and techniques. It shows better performance compared to both integrated inductor-based and capacitor-based voltage regulators. The results prove that the proposed set of voltage regulators offers a potential move towards easing the integration of voltage regulators on chip with a performance that approaches that of off-chip voltage regulators

Quantified Design Guidelines of Compact Active EMI Filters to Reduce the Common-Mode Conducted Emissions

Department of Electrical EngineeringIn switching mode power supplies (SMPS), noise currents induced by the switching operation travel along the input power line and may, in turn, cause interference with other electronic systems, including the SMPS???s auxiliary circuit. The noise current, caused by the switching operation to convert the voltage, is the main source of the conducted emissions. The passive EMI filters (PEFs) composed of a common mode (CM) chokes, Y-capacitors, and X-capacitor are generally used to suppress the conducted emissions. However, the CM chokes are bulky and occupy a lot of room. Y-capacitors cause the undesired touch current flowing from the power lines to the earth GND. In this thesis, three types of active EMI filters (AEF) ??? 1) voltage-sense voltage compensation (VSVC); 2) voltage-sense current-compensation (VSCC); 3) current-sense current-compensation (CSCC) ??? have been proposed to help overcome the limitation of the PEFs. The proposed AEFs have been designed as the feed-forward or transformerless configurations to manufacture in the compact size. Each AEF is completely analyzed by using the equivalent circuit model. Based on the rigorous analysis, the design guidelines of each AEF are established. In the design guidelines, the practical issues regarding the stability and high-voltage immunity are also considered. The performance of each AEF is validated through the experiments using a vector network analyzer (VNA) and the CM-conducted emissions measurements. The feed-forward VSVC AEF is designed in a compact package to suppress CM-conducted emissions. The power line impedance is enlarged by the VSVC AEF and verified through the measurement. The VSVC AEF was installed in a 200W switching mode power supply (SMPS) board with 64 kHz and 110 kHz switching frequencies, demonstrating its usefulness by experiments. The performance degradation due to the magnetic saturation and the AEF grounding impedance was also analyzed and investigated The transformerless VSCC AEF is developed to avoid the degradation due to the magnetic saturation. The sensing and compensation part is realized by only the capacitors, and the push???pull amplifier is utilized to generate the compensation signal corresponding to the sensed noise. Furthermore, the protection circuits against the high-voltage transient are developed and applied into the AEF. The VSCC AEF is then implemented into a real 2.2 kW current resonant inverter, and the conducted emissions are reduced by 5dB to 25 dB at a frequency range from 150 kHz to 6 MHz. In addition, the AEF???s immunity against high-voltage transients is demonstrated by lightning surge tests. The CSCC AEF is designed as the symmetric structure using the capacitive coupling. The transformer with a small number of turns is utilized for the sensing transformer to avoid degradation due to the magnetic saturation. The CSCC AEF is also designed using the proposed design guidelines and employed into the real product. In the CM conducted emissions measurement, the CSCC AEF shows 5~20 dB noise attenuation from 150 kHz to 10 MHz. The degradation of the CSCC AEF due to the asymmetric structure is investigated by using the VNA measurements.ope

On-Chip Power Supply Noise: Scaling, Suppression and Detection

Design metrics such as area, timing and power are generally considered as the primary criteria in the design of modern day circuits, however, the minimization of power supply noise, among other noise sources, is appreciably more important since not only can it cause a degradation in these parameters but can cause entire chips to fail. Ensuring the integrity of the power supply voltage in the power distribution network of a chip is therefore crucial to both building reliable circuits as well as preventing circuit performance degradation. Power supply noise concerns, predicted over two decades ago, continue to draw significant attention, and with present CMOS technology projected to keep on scaling, it is shown in this work that these issues are not expected to diminish. This research also considers the management and on-chip detection of power supply noise. There are various methods of managing power supply noise, with the use of decoupling capacitors being the most common technique for suppressing the noise. An in-depth analysis of decap structures including scaling effects is presented in this work with corroborating silicon results. The applicability of various decaps for given design constraints is provided. It is shown that MOS-metal hybrid structures can provide a significant increase in capacitance per unit area compared to traditional structures and will continue to be an important structure as technology continues to scale. Noise suppression by means of current shifting within the clock period of an ALU block is further shown to be an additional method of reducing the minimum voltage observed on its associated supply. A simple, and area and power efficient technique for on-chip supply noise detection is also proposed