4,675 research outputs found

    Design and Fabrication of Vertically-Integrated CMOS Image Sensors

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    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors

    Towards Single-Chip Nano-Systems

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    Important scientific discoveries are being propelled by the advent of nano-scale sensors that capture weak signals from their environment and pass them to complex instrumentation interface circuits for signal detection and processing. The highlight of this research is to investigate fabrication technologies to integrate such precision equipment with nano-sensors on a single complementary metal oxide semiconductor (CMOS) chip. In this context, several demonstration vehicles are proposed. First, an integration technology suitable for a fully integrated flexible microelectrode array has been proposed. A microelectrode array containing a single temperature sensor has been characterized and the versatility under dry/wet, and relaxed/strained conditions has been verified. On-chip instrumentation amplifier has been utilized to improve the temperature sensitivity of the device. While the flexibility of the array has been confirmed by laminating it on a fixed single cell, future experiments are necessary to confirm application of this device for live cell and tissue measurements. The proposed array can potentially attach itself to the pulsating surface of a single living cell or a network of cells to detect their vital signs

    Design, fabrication and characterization of monolithic embedded parylene microchannels in silicon substrate

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    This paper presents a novel channel fabrication technology of bulk-micromachined monolithic embedded polymer channels in silicon substrate. The fabrication process favorably obviates the need for sacrifical materials in surface-micromachined channels and wafer-bonding in conventional bulk-micromachined channels. Single-layer-deposited parylene C (poly-para-xylylene C) is selected as a structural material in the microfabricated channels/columns to conduct life science research. High pressure capacity can be obtained in these channels by the assistance of silicon substrate support to meet the needs of high-pressure loading conditions in microfluidic applications. The fabrication technology is completely compatible with further lithographic CMOS/MEMS processes, which enables the fabricated embedded structures to be totally integrated with on-chip micro/nano-sensors/actuators/structures for miniaturized lab-on-a-chip systems. An exemplary process was described to show the feasibility of combining bulk micromachining and surface micromachining techniques in process integration. Embedded channels in versatile cross-section profile designs have been fabricated and characterized to demonstrate their capabilities for various applications. A quasi-hemi-circular-shaped embedded parylene channel has been fabricated and verified to withstand inner pressure loadings higher than 1000 psi without failure for micro-high performance liquid chromatography (µHPLC) analysis. Fabrication of a high-aspect-ratio (internal channel height/internal channel width, greater than 20) quasi-rectangular-shaped embedded parylene channel has also been presented and characterized. Its implementation in a single-mask spiral parylene column longer than 1.1 m in a 3.3 mm × 3.3 mm square size on a chip has been demonstrated for prospective micro-gas chromatography (µGC) and high-density, high-efficiency separations. This proposed monolithic embedded channel technology can be extensively implemented to fabricate microchannels/columns in high-pressure microfludics and high-performance/high-throughput chip-based micro total analysis systems (µTAS)

    Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs.

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    Because of the today's market demand for high-performance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-D planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration. Among the various choices, finding an optimal solution for system implementation dealt usually with cost, performance and other technological trade-off analysis at the system conceptual level. It has been identified that the decisions made within the first 20% of the total design cycle time will ultimately result up to 80% of the final product cost. In this paper, we discuss appropriate and realistic metric for performance and cost trade-off analysis both at system conceptual level (up-front in the design phase) and at implementation phase for verification in the three-dimensional integration. In order to validate the methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and discuss the pros and cons of each of them

    Pixel Detectors for Charged Particles

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    Pixel Detectors, as the current technology of choice for the innermost vertex detection, have reached a stage at which large detectors have been built for the LHC experiments and a new era of developments, both for hybrid and for monolithic or semi-monolithic pixel detectors is in full swing. This is largely driven by the requirements of the upgrade programme for the superLHC and by other collider experiments which plan to use monolithic pixel detectors for the first time. A review on current pixel detector developments for particle tracking and vertexing is given, comprising hybrid pixel detectors for superLHC with its own challenges in radiation and rate, as well as on monolithic, so-called active pixel detectors, including MAPS and DEPFET pixels for RHIC and superBelle.Comment: 19 pages, 23 drawings in 14 figure

    Method for fabricating vertically-offset interdigitated comb actuator device

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    The present invention relates to systems and methods for fabricating microscanners. The fabrication processes employed pursuant to some embodiments are compatible with well known CMOS fabrication techniques, allowing devices for control, monitoring and/or sensing to be integrated onto a single chip. Both one- and two-dimensional microscanners are described. Applications including optical laser surgery, maskless photolithography, portable displays and large scale displays are described

    CMOS Photodetectors

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