Self-Reconfigurable Analog Arrays: Off-The Shelf Adaptive Electronics for Space Applications

Development of analog electronic solutions for space avionics is expensive and lengthy. Lack of flexible analog devices, counterparts to digital Field Programmable Gate Arrays (FPGA), prevents analog designers from benefits of rapid prototyping. This forces them to expensive and lengthy custom design, fabrication, and qualification of application specific integrated circuits (ASIC). The limitations come from two directions: commercial Field Programmable Analog Arrays (FPAA) have limited variability in the components offered on-chip; and they are only qualified for best case scenarios for military grade (-55C to +125C). In order to avoid huge overheads, there is a growing trend towards avoiding thermal and radiation protection by developing extreme environment electronics, which maintain correct operation while exposed to temperature extremes (-180degC to +125degC). This paper describes a recent FPAA design, the Self-Reconfigurable Analog Array (SRAA) developed at JPL. It overcomes both limitations, offering a variety of analog cells inside the array together with the possibility of self-correction at extreme temperatures

Visual Spike-based Convolution Processing with a Cellular Automata Architecture

this paper presents a first approach for implementations which fuse the Address-Event-Representation (AER) processing with the Cellular Automata using FPGA and AER-tools. This new strategy applies spike-based convolution filters inspired by Cellular Automata for AER vision processing. Spike-based systems are neuro-inspired circuits implementations traditionally used for sensory systems or sensor signal processing. AER is a neuromorphic communication protocol for transferring asynchronous events between VLSI spike-based chips. These neuro-inspired implementations allow developing complex, multilayer, multichip neuromorphic systems and have been used to design sensor chips, such as retinas and cochlea, processing chips, e.g. filters, and learning chips. Furthermore, Cellular Automata is a bio-inspired processing model for problem solving. This approach divides the processing synchronous cells which change their states at the same time in order to get the solution.Ministerio de Educación y Ciencia TEC2006-11730-C03-02Ministerio de Ciencia e Innovación TEC2009-10639-C04-02Junta de Andalucía P06-TIC-0141

Reconfigurable FIR Filter in FPGA

Finite Impulse Response (FIR) filters are widely used in Digital Signal Processing (DSP) systems. The throughput of real-time, FIR filters is limited by the processing capability of its implementation. Software implementations are very flexible but the inherent sequential execution of programs makes them slow. The fastest FIR filters are those implemented in dedicated hardware, but these systems are usually fixed and modifications to the filter are not possible. This paper presents the design and implementation of a Field-Programmable Gate-Array (FPGA)-based, FIR filter. By exploiting the field-programmability of FPGAs it is possible to create different filters with fixed functionality, or even create adaptive filters whose parameters are adjusted in real-time by some intelligent algorithm

A VHDL Core for Intrinsic Evolution of Discrete Time Filters with Signal Feedback

The design of an Evolvable Machine VHDL Core is presented, representing a discrete-time processing structure capable of supporting control system applications. This VHDL Core is implemented in an FPGA and is interfaced with an evolutionary algorithm implemented in firmware on a Digital Signal Processor (DSP) to create an evolvable system platform. The salient features of this architecture are presented. The capability to implement IIR filter structures is presented along with the results of the intrinsic evolution of a filter. The robustness of the evolved filter design is tested and its unique characteristics are described

Accelerating FPGA-based evolution of wavelet transform filters by optimized task scheduling

Adaptive embedded systems are required in various applications. This work addresses these needs in the area of adaptive image compression in FPGA devices. A simplified version of an evolution strategy is utilized to optimize wavelet filters of a Discrete Wavelet Transform algorithm. We propose an adaptive image compression system in FPGA where optimized memory architecture, parallel processing and optimized task scheduling allow reducing the time of evolution. The proposed solution has been extensively evaluated in terms of the quality of compression as well as the processing time. The proposed architecture reduces the time of evolution by 44% compared to our previous reports while maintaining the quality of compression unchanged with respect to existing implementations. The system is able to find an optimized set of wavelet filters in less than 2 min whenever the input type of data changes

Absolutely free extrinsic evolution of passive low-pass filter

Evolutionary electronics is a brunch of evolvable hardware, where the evolutionary algorithm is applied towards electronic circuits. The success of evolutionary search most of all depends on variable length representation methodology. The low-pass filter is a standard task in evolutionary electronics to start with. The results of evolution enable one to qualify whether the methodology is good for further experiments. In this paper the maximum freedom for evolutionary search has been proclaimed as a main target during development of new VLR methodology. The introduction of R-support elements enables to perform an unconstrained evolution of analogue circuits for the first time. The proposed algorithm has been tested on the example of analogue low-pass filter. The experimental results demonstrate that the evolved filter is comparable with filters evolved previously using genetic programming and genetic algorithms techniques. The obtained results are compared in details with low-pass filters previously designed

Constrained and unconstrained evolution of “ LCR” low-pass filters with oscillating length representation

The unconstrained evolution has already been applied in the past towards design of digital circuits, and extraordinary results have been obtained, including generation of circuits with smaller number of electronic components. In this paper both constrained and unconstrained evolutions, blended with oscillating length genotype sweeping strategy, are applied towards design of analogue “ LCR” circuits. The comparison of both evolutions is made and the promising results are obtained. The new algorithm has produced the best results in terms of quality of the circuits evolved and evolutionary resources required. It differs from previous ones by its simplicity and represents one of the first attempts to apply Evolutionary Strategy towards the analogue circuit design. The obtained results are compared in details with low-pass filters previously designed