A Construction Kit for Efficient Low Power Neural Network Accelerator Designs

Implementing embedded neural network processing at the edge requires efficient hardware acceleration that couples high computational performance with low power consumption. Driven by the rapid evolution of network architectures and their algorithmic features, accelerator designs are constantly updated and improved. To evaluate and compare hardware design choices, designers can refer to a myriad of accelerator implementations in the literature. Surveys provide an overview of these works but are often limited to system-level and benchmark-specific performance metrics, making it difficult to quantitatively compare the individual effect of each utilized optimization technique. This complicates the evaluation of optimizations for new accelerator designs, slowing-down the research progress. This work provides a survey of neural network accelerator optimization approaches that have been used in recent works and reports their individual effects on edge processing performance. It presents the list of optimizations and their quantitative effects as a construction kit, allowing to assess the design choices for each building block separately. Reported optimizations range from up to 10'000x memory savings to 33x energy reductions, providing chip designers an overview of design choices for implementing efficient low power neural network accelerators

Magnetic and Spin Devices

As the scaling of electronic semiconductor devices displays signs of saturation, the main focus of research in microelectronics is shifting towards finding new computing paradigms. Electron spin offers additional functionality to digital charge-based devices. Several fundamental problems, including spin injection to a semiconductor, spin propagation and relaxation, and spin manipulation by the gate voltage, have been successfully resolved to open a path towards spin-based reprogrammable electron switches. Devices employing electron spin are nonvolatile; they are able to preserve the stored information without external power. Emerging nonvolatile devices are electrically addressable, possess a simple structure, and offer endurance and speed superior to flash memory. Having nonvolatile memory very close to CMOS offers a prospect of data processing in the nonvolatile segment, where the same devices are used to store and process the information. This opens perspectives for conceptually new low-power computing paradigms within Artificial Intelligence of Things (AIoT). This Special Issue focuses on all topics related to spintronic devices such as spin-based switches, magnetoresistive memories, energy harvesting devices, and sensors that can be employed in in-memory computing concepts and in Artificial Intelligence

Adaptive extreme edge computing for wearable devices

Wearable devices are a fast-growing technology with impact on personal healthcare for both society and economy. Due to the widespread of sensors in pervasive and distributed networks, power consumption, processing speed, and system adaptation are vital in future smart wearable devices. The visioning and forecasting of how to bring computation to the edge in smart sensors have already begun, with an aspiration to provide adaptive extreme edge computing. Here, we provide a holistic view of hardware and theoretical solutions towards smart wearable devices that can provide guidance to research in this pervasive computing era. We propose various solutions for biologically plausible models for continual learning in neuromorphic computing technologies for wearable sensors. To envision this concept, we provide a systematic outline in which prospective low power and low latency scenarios of wearable sensors in neuromorphic platforms are expected. We successively describe vital potential landscapes of neuromorphic processors exploiting complementary metal-oxide semiconductors (CMOS) and emerging memory technologies (e.g. memristive devices). Furthermore, we evaluate the requirements for edge computing within wearable devices in terms of footprint, power consumption, latency, and data size. We additionally investigate the challenges beyond neuromorphic computing hardware, algorithms and devices that could impede enhancement of adaptive edge computing in smart wearable devices

Fault-tolerant satellite computing with modern semiconductors

Miniaturized satellites enable a variety space missions which were in the past infeasible, impractical or uneconomical with traditionally-designed heavier spacecraft. Especially CubeSats can be launched and manufactured rapidly at low cost from commercial components, even in academic environments. However, due to their low reliability and brief lifetime, they are usually not considered suitable for life- and safety-critical services, complex multi-phased solar-system-exploration missions, and missions with a longer duration. Commercial electronics are key to satellite miniaturization, but also responsible for their low reliability: Until 2019, there existed no reliable or fault-tolerant computer architectures suitable for very small satellites. To overcome this deficit, a novel on-board-computer architecture is described in this thesis.Robustness is assured without resorting to radiation hardening, but through software measures implemented within a robust-by-design multiprocessor-system-on-chip. This fault-tolerant architecture is component-wise simple and can dynamically adapt to changing performance requirements throughout a mission. It can support graceful aging by exploiting FPGA-reconfiguration and mixed-criticality.  Experimentally, we achieve 1.94W power consumption at 300Mhz with a Xilinx Kintex Ultrascale+ proof-of-concept, which is well within the powerbudget range of current 2U CubeSats. To our knowledge, this is the first COTS-based, reproducible on-board-computer architecture that can offer strong fault coverage even for small CubeSats.European Space AgencyComputer Systems, Imagery and Medi

Tunnel Field Effect Transistors:from Steep-Slope Electronic Switches to Energy Efficient Logic Applications

The aim of this work has been the investigation of homo-junction Tunnel Field Effect Transistors starting from a compact modelling perspective to its possible applications. Firstly a TCAD based simulation study is done to explain the main device characteristics. The main differences of a Tunnel FET with respect to a conventional MOSFET is pointed out and the differences have been explained. A compact DC/AC model has been developed which is capable of describing the I-V characteristics in all regimes of operation. The model takes in to account ambi-polarity, drain side breakdown and all tunneling related physics. A temperature dependence is also added to the model to study the temperature independent behavior of tunneling. The model was further implemented in a Verilog-A based circuit simulator. Following calibration to experimental results of Silicon and strained-Silicon TFETs, the model has been also used to benchmark against a standard CMOS node for digital and analog applications. The circuits built with Tunnel FETs showed interesting temperature behavior which was superior to the compared CMOS node. In the same work, we also explore and propose solutions for using TFETs for low power memory applications. Both volatile and non-volatile memory concepts are investigated and explored. The application of a Tunnel FET as a capacitor-less memory has been experimentally demonstrated for the first time. New device concepts have been proposed and process flows for the same are developed to realize them in the clean room in EPFL

Dependable Embedded Systems

This Open Access book introduces readers to many new techniques for enhancing and optimizing reliability in embedded systems, which have emerged particularly within the last five years. This book introduces the most prominent reliability concerns from today’s points of view and roughly recapitulates the progress in the community so far. Unlike other books that focus on a single abstraction level such circuit level or system level alone, the focus of this book is to deal with the different reliability challenges across different levels starting from the physical level all the way to the system level (cross-layer approaches). The book aims at demonstrating how new hardware/software co-design solution can be proposed to ef-fectively mitigate reliability degradation such as transistor aging, processor variation, temperature effects, soft errors, etc. Provides readers with latest insights into novel, cross-layer methods and models with respect to dependability of embedded systems; Describes cross-layer approaches that can leverage reliability through techniques that are pro-actively designed with respect to techniques at other layers; Explains run-time adaptation and concepts/means of self-organization, in order to achieve error resiliency in complex, future many core systems

Design and Evaluation of a 28-nm FD-SOI STT-MRAM for Ultra-Low Power microcontrollers

International audienceThe complexity of embedded devices increases as today's applications request always more services. However, the power consumption of systems-on-chip has significantly increased due to the high-density integration and the high leakage power of current CMOS transistors. To address these issues, emerging technologies are considered. Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is seen as a promising alternative solution to traditional memories thanks to its negligible leakage current, high density, and non-volatility. In this work, we present the design and evaluation of a 128 kB STT-RAM in 28-nm FD-SOI technology with SRAM-like interface for ultra-low power microcontrollers. With 0.9 pJ/bit read in 5 ns and 3 pJ/bit write in 10 ns, this embedded non-volatile memory is suitable for devices that run at frequencies under 100 MHz. Considering low-power application with duty-cycled behaviour, we evaluate the STT-MRAM as a replacement of embedded Flash and SRAM by comparing single and multi-memory architecture scenarios

Intelligent Circuits and Systems

ICICS-2020 is the third conference initiated by the School of Electronics and Electrical Engineering at Lovely Professional University that explored recent innovations of researchers working for the development of smart and green technologies in the fields of Energy, Electronics, Communications, Computers, and Control. ICICS provides innovators to identify new opportunities for the social and economic benefits of society.　 This conference bridges the gap between academics and R&D institutions, social visionaries, and experts from all strata of society to present their ongoing research activities and foster research relations between them. It provides opportunities for the exchange of new ideas, applications, and experiences in the field of smart technologies and finding global partners for future collaboration. The ICICS-2020 was conducted in two broad categories, Intelligent Circuits & Intelligent Systems and Emerging Technologies in Electrical Engineering