1,143 research outputs found

    Performance realization of Bridge Model using Ethernet-MAC for NoC based system with FPGA Prototyping

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    The System on Chip (SoC) integrates the number of processing elements (PE) with different application requirements on a single chip. The SoC uses bus-based interconnection with shared memory access. However, buses are not scalable and limited to particular interface protocol. To overcome these problems, The Network on Chip (NoC) is an emerging interconnect solution with a scalable and reliable solution over SoC. The bridge model is essential to communicate the NoC based system on SoC. In this article, a cost-effective and efficient bridge model with ethernet-MAC is designed and also the placement of the bride with NoC based system is prototyped on Artix-7 FPGA. The Bridge model mainly contains FIFO modules, Serializer and de-serializer, priority-based arbiter with credit counter, packet framer and packet parser with Ethernet-MAC transceiver Module. The bridge with a single router and different sizes of the NoC based systems with mesh topology are designed using adaptive-XY routing. The performance metrics are evaluated for bridge with NoC in terms of average latency and maximum throughput for different Packet Injection Rate (PIR)

    Real-Time Guarantees in Routerless Networks-on-Chip

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    This paper considers the use of routerless networks-on-chip as an alternative on-chip interconnect for multiprocessor systems requiring hard real-time guarantees for inter-processor communication. It presents a novel analytical framework that can provide latency upper bounds to real-time packet flows sent over routerless networks-on-chip, and it uses that framework to evaluate the ability of such networks to provide real-time guarantees. Extensive comparative analysis is provided, considering different architectures for routerless networks and a state-of-the-art wormhole network based on priority-preemptive routers as a baseline

    Technical Design Report for the PANDA Micro Vertex Detector

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    This document illustrates the technical layout and the expected performance of the Micro Vertex Detector (MVD) of the PANDA experiment. The MVD will detect charged particles as close as possible to the interaction zone. Design criteria and the optimisation process as well as the technical solutions chosen are discussed and the results of this process are subjected to extensive Monte Carlo physics studies. The route towards realisation of the detector is outlined

    Wood Properties and Processing

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    Wood-based materials are CO2-neutral, renewable, and considered to be environmentally friendly. The huge variety of wood species and wood-based composites allows a wide scope of creative and esthetic alternatives to materials with higher environmental impacts during production, use and disposal. Quality of wood is influenced by the genetic and environmental factors. One of the emerging uses of wood are building and construction applications. Modern building and construction practices would not be possible without use of wood or wood-based composites. The use of composites enables using wood of lower quality for the production of materials with engineered properties for specific target applications. Even more, the utilization of such reinforcing particles as carbon nanotubes and nanocellulose enables development of a new generation of composites with even better properties. The positive aspect of decomposability of waste wood can turn into the opposite when wood or wood-based materials are exposed to weathering, moisture oscillations, different discolorations, and degrading organisms. Protective measures are therefore unavoidable for many outdoor applications. Resistance of wood against different aging factors is always a combined effect of toxic or inhibiting ingredients on the one hand, and of structural, anatomical, or chemical ways of excluding moisture on the other
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