From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

Network Interface Design for Network-on-Chip

In the culture of globalized integrated circuit (IC, a.k.a chip) production, the use of Intellectual Property (IP) cores, computer aided design tools (CAD) and testing services from un-trusted vendors are prevalent to reduce the time to market. Unfortunately, the globalized business model potentially creates opportunities for hardware tampering and modification from adversary, and this tampering is known as hardware Trojan (HT). Network-on-chip (NoC) has emerged as an efficient on-chip communication infrastructure. In this work, the security aspects of NoC network interface (NI), one of the most critical components in NoC will be investigated and presented. Particularly, the NI design, hardware attack models and countermeasures for NI in a NoC system are explored. An OCP compatible NI is implemented in an IBM0.18ìm CMOS technology. The synthesis results are presented and compared with existing literature. Second, comprehensive hardware attack models targeted for NI are presented from system level to circuit level. The impact of hardware Trojans on NoC functionality and performance are evaluated. Finally, a countermeasure method is proposed to address the hardware attacks in NIs

Processing of FMCW 24/120GHz Radar Signals

Tato práce dokumentuje návrh, realizaci a funkcionalitu zařízení vzorkující základní pásmo radaru, jeho firmware k akvizici dat a přenos přes USB a programové vybavení pro osobní počítač. Systém byl navrženo pro testovací sadu FMCW radaru Silicon Radar Easy. Důležitá rozhodnutí provedená v procesu návrhu jsou poskytnuty se srovnáním s altenativami pro poskytnutí kontextu a usnadnění vývoje dalších zařízení. Detekce vzdálenosti a rychlosti a ekvalizace I/Q větví jsou krátce probrány, spolu s minimálními systémovými požadavky na zcela zabudované zpracování radarových signálů.This thesis documents the design and performance of baseband sampling hardware, its data acquisition, and USB transmitting firmware, and PC-side reception software, designed for the Silicon Radar Easy FMCW radar module evaluation kit. Major design decision explanations are provided with comparisons to alternatives to provide context and ease further development. Range and velocity detection and I/Q imbalance equalization are briefly discussed, as well as the minimum system requirements for fully embedded signal processing

Design and Validation of Network-on-Chip Architectures for the Next Generation of Multi-synchronous, Reliable, and Reconfigurable Embedded Systems

NETWORK-ON-CHIP (NoC) design is today at a crossroad. On one hand, the design principles to efficiently implement interconnection networks in the resource-constrained on-chip setting have stabilized. On the other hand, the requirements on embedded system design are far from stabilizing. Embedded systems are composed by assembling together heterogeneous components featuring differentiated operating speeds and ad-hoc counter measures must be adopted to bridge frequency domains. Moreover, an unmistakable trend toward enhanced reconfigurability is clearly underway due to the increasing complexity of applications. At the same time, the technology effect is manyfold since it provides unprecedented levels of system integration but it also brings new severe constraints to the forefront: power budget restrictions, overheating concerns, circuit delay and power variability, permanent fault, increased probability of transient faults. Supporting different degrees of reconfigurability and flexibility in the parallel hardware platform cannot be however achieved with the incremental evolution of current design techniques, but requires a disruptive approach and a major increase in complexity. In addition, new reliability challenges cannot be solved by using traditional fault tolerance techniques alone but the reliability approach must be also part of the overall reconfiguration methodology. In this thesis we take on the challenge of engineering a NoC architectures for the next generation systems and we provide design methods able to overcome the conventional way of implementing multi-synchronous, reliable and reconfigurable NoC. Our analysis is not only limited to research novel approaches to the specific challenges of the NoC architecture but we also co-design the solutions in a single integrated framework. Interdependencies between different NoC features are detected ahead of time and we finally avoid the engineering of highly optimized solutions to specific problems that however coexist inefficiently together in the final NoC architecture. To conclude, a silicon implementation by means of a testchip tape-out and a prototype on a FPGA board validate the feasibility and effectivenes

Real-time frequency measurement based on parallel pipeline FFT for time-stretched acquisition system

Real-time frequency measurement for non-repetitive and statistically rare signals are challenging problems in the electronic measurement area, which places high demands on the bandwidth, sampling rate, data processing and transmission capabilities of the measurement system. The time-stretching sampling system overcomes the bandwidth limitation and sampling rate limitation of electronic digitizers, allowing continuous ultra-high-speed acquisition at refresh rates of billions of frames per second. However, processing the high sampling rate signals of hundreds of GHz is an extremely challenging task, which becomes the bottleneck of the real-time analysis for non-stationary signals. In this work, a real-time frequency measurement system is designed based on a parallel pipelined FFT structure. Tens of FFT channels are pipelined to process the incoming high sampling rate signals in sequence, and a simplified parabola fitting algorithm is implemented in the FFT channel to improve the frequency precision. The frequency results of these FFT channels are reorganized and finally uploaded to an industrial personal computer for visualization and offline data mining. A real-time transmission datapath is designed to provide a high throughput rate transmission, ensuring the frequency results are uploaded without interruption. Several experiments are performed to evaluate the designed real-time frequency measurement system, the input signal has a bandwidth of 4 GHz, and the repetition rate of frames is 22 MHz. Experimental results show that the frequency of the signal can be measured at a high sampling rate of 20 GSPS, and the frequency precision is better than 1 MHz.Comment: 11 pages, 14 figure

Coupling of a Powerline Communication Modem to an Industrial Fieldbus Network

In a broad and heterogeneous industrial communications environment, the need of having flexibility as well as maintaining the reliability and low cost has pushed the researchers to look for new possibilities and market opportunities to cover all the needs. Actual industrial systems are needed of at least two ways of inputs: power input, for the system operation, and data input for controlling, testing and administrating the system. The main restrictions, that actual systems and networks have, are low flexibility and, sometimes, considerable expenses in terms on maintenance. But also they have advantages, e.g. low response time, high reliability, wide and highly known architecture etc. In this background, grows the thought of increasing the flexibility without impacting such important aspects as response time or reliability. On the industrial communication protocols, Ethernet POWERLINK standard is one of the existing protocols in the market. Ethernet POWERLINK is a real-time industrial communication protocol based on Ethernet standard, which is used for controlling and commanding several sensors and actuators with high speed, time-synchronization and reliability, minimizing the global system latency. The main aim of this project is to reach a balanced solution by joining both power and data inputs in just one cable that allows an increase in the flexibility, as well as decrease in the maintenance costs, restraining the response time and achieving compatibility with a wide spread standard as is Ethernet.Puche Planells, J. (2014). Coupling of a Powerline Communication Modem to an Industrial Fieldbus Network. http://hdl.handle.net/10251/46618.Archivo delegad