1,691 research outputs found

    CMOS ring oscillator delay cell performance: a comparative study

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    A common voltage-controlled oscillator (VCO) architecture used in the phase locked loop (PLL) is the ring oscillator (RO). RO consist of number of inverters cascaded together as the input of the first stage connected to the output of the last stage. It is important to design the RO to be work at desired frequency depend on application with low power consumption. This paper presents a review the performance evaluation of different delay cell topologies the implemented in the ring oscillator. The various topologies analyzed includes current starved delay cell, differential delay cell and current follower cell. Performance evaluation includes frequency range, frequency stability, phase noise and power consumption had been reviewed and comparison of different topologies has been discussed. It is observed that starved current delay cell have lower power consumption and the different of the frequency range is small as compared to other type of delay cell

    Development and characterisation of a near-infrared femtosecond optical parametric oscillator frequency comb

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    This thesis describes a 280 MHz MgO:PPLN-based optical parametric oscillator (OPO) synchronously pumped by a 50 fs Ti:sapphire laser to produce ultrafast pulses in the near-infrared. The OPO tuned over a wavelength range from 1450 - 1550 nm and 1624 - 1750 nm for the signal and idler respectively. The carrier-envelope-offset (CEO) frequency of the signal pulses was stabilised to a 10 MHz reference frequency without f-2f self-referencing, with an RMS phase variation of 0.56 rad over an observation time of 1 second. The relative intensity noise was measured for the CEO-stabilised OPO over an observation time of 64 seconds as 0.04%. The repetition frequency of the OPO was stabilised to 280 MHz using a frequency synthesiser at the eighth harmonic (2.24 GHz). This locking loop had an RMS phase variation of 0.98 mrad over a 1 second observation time. The CEO- and repetition frequencies were then locked simultaneously to a synthesiser referenced to a Rb-disciplined source, to generate a fully stabilised 1.5 μm frequency comb with an absolute uncertainty in comb mode position of 110 Hz. The upper limit for the fractional instability for a comb mode at 200 THz was found to be 2 x 10-11, limited by the stability of the Rb reference. A five-fold increase in comb mode spacing to 1.4 GHz was demonstrated with the stabilised frequency comb. This was achieved using a passive filter cavity, stabilised to a transmission peak via dither locking. The FWHM bandwidth of the optical spectrum for the filtered frequency comb was reduced to 8 nm, however no increase in comb linewidth was observed. An additional experiment was carried out where an external cavity diode laser was frequency-stabilised to a saturated absorption peak in Rb at 780.2 nm using dither locking, providing an optical frequency reference for future OPO frequency combs

    Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

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    Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort

    A Low-Power BFSK/OOK Transmitter for Wireless Sensors

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    In recent years, significant improvements in semiconductor technology have allowed consistent development of wireless chipsets in terms of functionality and form factor. This has opened up a broad range of applications for implantable wireless sensors and telemetry devices in multiple categories, such as military, industrial, and medical uses. The nature of these applications often requires the wireless sensors to be low-weight and energy-efficient to achieve long battery life. Among the various functions of these sensors, the communication block, used to transmit the gathered data, is typically the most power-hungry block. In typical wireless sensor networks, transmission range is below 10 meters and required radiated power is below 1 milliwatt. In such cases, power consumption of the frequency-synthesis circuits prior to the power amplifier of the transmitter becomes significant. Reducing this power consumption is currently the focus of various research endeavors. A popular method of achieving this goal is using a direct-modulation transmitter where the generated carrier is directly modulated with baseband data using simple modulation schemes. Among the different variations of direct-modulation transmitters, transmitters using unlocked digitally-controlled oscillators and transmitters with injection or resonator-locked oscillators are widely investigated because of their simple structure. These transmitters can achieve low-power and stable operation either with the help of recalibration or by sacrificing tuning capability. In contrast, phase-locked-loop-based (PLL) transmitters are less researched. The PLL uses a feedback loop to lock the carrier to a reference frequency with a programmable ratio and thus achieves good frequency stability and convenient tunability. This work focuses on PLL-based transmitters. The initial goal of this work is to reduce the power consumption of the oscillator and frequency divider, the two most power-consuming blocks in a PLL. Novel topologies for these two blocks are proposed which achieve ultra-low-power operation. Along with measured performance, mathematical analysis to derive rule-of-thumb design approaches are presented. Finally, the full transmitter is implemented using these blocks in a 130 nanometer CMOS process and is successfully tested for low-power operation

    Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

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    Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort

    Analytic design of spaceborne axial injection cross-field amplifiers Final report

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    S band crossed-field amplifier suitable for satellite television relay system

    Optical multi-stable operations of coupled lasers

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    Optical memories are optical bi(multi-)stable systems whose states can be switched all optically. Acting as a fundamental building block for digital optical signal processing, they have received considerable attention. Many types of optical memories have been explored, which all have in common that they are optical storage elements with two states. Multi-stable optical logic building blocks are interesting for applications in telecommunication systems, since they have potential to process a large number of wavelength channels in parallel. In this thesis, we present two types of multi-stable operation of coupled lasers. The first one is based on coupled ring lasers, which share a single active element and a feedback arm. A single ring laser with feedback can be regarded as an oscillator, since the intensity of the lasing light in the lasing cavity is periodically oscillating. When two such oscillators are coupled together, sharing the same active element and the same feedback arm, they synchronize in a common oscillation frequency if their individual oscillation periodicities are close to each other; otherwise they show bistability between the two oscillators. Switching between different stable states can be realized by injecting external light, in this sense, the system act as an optical memory. Moreover, this concept can easily realize multi-state operation, since only one active element is required. An eight-state optical memory is demonstrated. The second type of multi-stable operation of coupled lasers is based on serially interconnected lasers using the principle of gain quenching. The light from the dominant laser suppresses its neighboring lasers through gain saturation, but still receives amplification by the active element of the suppressed lasers, compensating for coupling losses. This light passes through each of the successive lasers, simultaneously suppressing and being amplified. By this mechanism all the other lasers are suppressed. Only one of the lasers can lase at a time, thus the state of the optical memory is determined by the wavelength of the dominant laser, as same as the first type. A five-state optical memory based on this concept is experimentally demonstrated. Moreover, we use the optical memories as a fundamental logic unit to realize sophisticated optical logic. We present an optical shift register that consists of two serially connected optical memories driven by common clock pulses. The concept is demonstrated at an operation speed of 20 kHz, which is limited by the laser cavities implemented by 10 meter long fiber pigtailed components. Furthermore, we cascade the optical shift register and an optical XOR gate to realize an optical pseudorandom number generator based on optical memories

    Novel Transistor Resistance Variation-based Physical Unclonable Functions with On-Chip Voltage-to-Digital Converter Designed for Use in Cryptographic and Authentication Applications

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    Security mechanisms such as encryption, authentication, and feature activation depend on the integrity of embedded secret keys. Currently, this keying material is stored as digital bitstrings in non-volatile memory on FPGAs and ASICs. However, secrets stored this way are not secure against a determined adversary, who can use specialized probing attacks to uncover the secret. Furthermore, storing these pre-determined bitstrings suffers from the disadvantage of not being able to generate the key only when needed. Physical Unclonable Functions (PUFs) have emerged as a superior alternative to this. A PUF is an embedded Integrated Circuit (IC) structure that is designed to leverage random variations in physical parameters of on-chip components as the source of entropy for generating random and unique bitstrings. PUFs also incorporate an on-chip infrastructure for measuring and digitizing these variations in order to produce bitstrings. Additionally, PUFs are designed to reproduce a bitstring on-demand and therefore eliminate the need for on-chip storage. In this work, two novel PUFs are presented that leverage the random variations observed in the resistance of transistors. A thorough analysis of the randomness, uniqueness and stability characteristics of the bitstrings generated by these PUFs is presented. All results shown are based on an exhaustive testing of a set of 63 chips designed with numerous copies of the PUFs on each chip and fabricated in a 90nm nine-metal layer technology. An on-chip voltage-to-digital conversion technique is also presented and tested on the set of 63 chips. Statistical results of the bitstrings generated by the on-chip digitization technique are compared with that of the voltage-derived bitstrings to evaluate the efficacy of the digitization technique. One of the most important quality metrics of the PUF and the on-chip voltage-to-digital converter, the stability, is evaluated through a lengthy temperature-voltage testing over the range of -40C to +85C and voltage variations of +/- 10% of the nominal supply voltage. The stability of both the bitstrings and the underlying physical parameters is evaluated for the PUFs using the data collected from the hardware experiments and supported with software simulations conducted on the devices. Several novel techniques are proposed and successfully tested that address known issues related to instability of PUFs to changing temperature and voltage conditions, thus rendering our PUFs more resilient to these changing conditions faced in practical use. Lastly, an analysis of the stability to changing temperature and voltage variations of a third PUF that leverages random variations in the resistance of the metal wires in the power and ground grids of a chip is also presented

    Versatile femtosecond optical parametric oscillator frequency combs for metrology

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    This thesis addresses the development of broadly tunable, high repetition rate frequency combs in the mid-IR region. A novel PPKTP crystal design was used to provide phasematching for parametric oscillation and simultaneously give efficient pump+idler sum-frequency generation (SFG). This innovation enabled a fully stabilized idler comb from a 333-MHz femtosecond optical parametric oscillator to be generated in which the carrier envelope offset frequency fCEO together with the repetition frequency fREP were stabilised. This OPO platform was then extended to demonstrate, via harmonic pumping, a fully stabilized 1-GHz OPO frequency comb from a 333-MHz pump laser. Next, an alternative route to a 1-GHz OPO comb was investigated by synchronously pumping an OPO directly with a 1-GHz Ti:sapphire laser. Here the comb was fully stabilized for the signal, idler and pump pulses by using a narrow linewidth CW diode laser developed for the project and whose design is also presented. A further increase in the comb mode spacing was performed with a Fabry-Pérot cavity. A stabilised cavity was used to filter 1.5 m signal pulses from a 333-MHz repetition rate OPO frequency comb to yield a 10-GHz comb. The length of the Fabry-Pérot cavity was dither locked to a single-frequency ECDL and later on directly to the OPO frequency comb. Finally the 333-MHz OPO comb was demonstrated in an optical frequency metrology experiment. The frequency comb mode number and the absolute frequency of a narrow-linewidth CW laser were measured and the performance of the OPO comb was found to be comparable to that of a commercial fibre laser comb used as a benchmark in the experiment
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