COMPARAÇÃO DE DESEMPENHO ENTRE ARBITRAGEM ROUND-ROBIN E ARBITRAGEM ROUND-ROBIN COM CANAIS VIRTUAIS EM REDES-EM-CHIP

Communication between components within a chip is essentialfor tasks and deadlines can be met. Network-to-Chipcommunication architectures have become a great option toreplace the bus in this task due to its inherent scalability.One of the One component that may impact the timing ofdata arrival is the arbitration scheme of choice, as the arbitratorshave the function of scheduling packets to be sent tothe next router, depending on some priority criteria. Thispaper focuses on comparing performance between two arbitrationschemes, Round-Robin and virtual channels. Tothis end, dierent trac patterns and dierent injection ratesare tested. Results show that the use of virtual channelscan provide more optimized latency gain solutions and aretherefore suitable for applications with more restricted timeconstraints.A comunicação entre componentes dentro de um chip e essencial para que tarefas e prazos possam ser cumpridos. Arquiteturas de comunicação do tipo Redes-em-Chip tornaram-se uma ótima opção para substituir o barramento nesta tarefa, em função de sua inerente escalabilidade. Um dos componentes que pode causar impacto no tempo para a chegada dos dados e o esquema de arbitragem escolhida, uma vez que os árbitros tem a função de escalonar pacotes a serem enviados para o próximo roteador, em função de um algum critério de prioridade. Este artigo foca na comparação de desempenho entre dois esquemas de arbitragem, Round-Robin e canais virtuais. Para tanto, são testados diferentes padrões de tráfego e diferentes taxas de injeção. Resultados mostram que o uso de canais virtuais pode fornecer soluções mais otimizadas em ganhos de latência sendo portanto, indicados para aplicações com restrições temporais mais restritas

Optimierung der Energie und Power getriebenen Architekturexploration für Multicore und heterogenes System on Chip

The contribution of this work builds on top of the established virtual prototype platforms to improve both SoC design quality and productivity. Initially, an automatic system-level power estimation framework was developed to address the critical issue of early power estimation in SoC design. The estimation framework models the static and dynamic power consumption of the hardware components. These models are created from the normalized values of the basic design components of SoC, obtained through one-time power simulation of RTL hardware models. The framework allows dynamic technology node reconfiguration for power estimation models. Its instantaneous power reporting aids the detection of possible hotspot early into the design process. Adding this additional data in conjunction with a steadily growing design space of complex heterogeneous SoC, finding the right parameter configuration is a challenging and laborious task for a system-level designer. This work addresses this bottleneck by optimizing the design space exploration (DSE) process for MPSoC design. An automatic DSE framework for virtual platforms (VPs) was developed which is flexible and allows the selection optimal parameter configuration without pre-existing knowledge. To reduce exploration time, the framework is equipped with several multi-objective optimization techniques based on simulated annealing and a genetic algorithm. Lastly, to aid HW/SW partitioning at system-level, a flexible and automated workflow (SW2TLM) is presented. It allows the designer to explore various possible partitioning scenarios without going into depth of the hardware architecture complexity and software integration. The framework generates system-level hardware accelerators from corresponding functionality encoded in the software code and integrates them into the VP. Power consumption and time speedups of acceleration is reported to the designer, which further increases the quality and productivity of the development process towards the final architecture. The presented tools are evaluated using a state-of-the-art VP for a range of single and multi-core applications. Viewing the energy delay product, a reduction in exploration time was recorded at approximately 62% (worst case), maintaining optimal parameter accuracy of 90% compared to previous techniques. While the SW2TLM further increases the exploration versatility by combining modern high-level synthesis with system-level architectural exploration.Der Beitrag dieser Arbeit baut auf dem etablierten Konzept der virtuellen Prototyp (VP) Plattformen auf, um die Qualität und die Produktivität des Entwurfsprozesses zu verbessern. Zunächst wurde ein automatisches System-Level-Framework entwickelt, um Verlustleistungsabschätzung für SoC-Designs in einer deutlich früheren Entwicklungsphase zu ermöglichen. Hierfür werden statischen und dynamischen Energieverbrauchsanteile individueller Hardwareelemente durch ein abstraktes Modell ausgedrückt. Das Framework ermöglicht eine dynamische Anpassung des Technologieknotens sowie die Integration neuer Leistungsmodelle für Drittanbieterkomponenten. Die kontinuierliche Erfassung der Energieverbrauchseigenschaften und ihre grafische Darstellung Benutzeroberfläche unterstützt zusätzlich die frühzeitige Identifikation möglicher Hotspots. Durch die Bereitstellung zusätzlicher Daten, in Verbindung mit einem stetig wachsenden Entwurfsraum komplexer SoCs, ist die Identifikation der richtigen Parameterkonfiguration eine zeitintensive Aufgabe. Die vorgelegten Konzepte erlauben eine gesteigerte Automatisierung des Explorationsprozesses. Techniken der mehrdimensionalen Optimierung, basierend auf Simulated Annealing und genetischer Algorithmen erlauben die Identifikation von geeigneten Konfigurationen ohne vorheriges Wissen oder Erfahrungswerte Schließlich wurde zur Unterstützung der HW/SW -Partitionierung auf System-Ebene ein flexibler und automatisierter Workflow entwickelt. Er ermöglicht es dem Designer verschiedene mögliche Partitionierungsszenarien zu untersuchen, ohne sich in die Komplexität der Hardwarearchitektur und der Softwareintegration zu vertiefen. Das Framework erzeugt abstrakte Beschleunigermodelle aus entsprechenden Softwarefunktionen und integriert sie nahtlos in den ausführbare VP. Detaillierte Daten zum Energieverbrauch, Beschleunigungsfaktor und Kommunikationsoverhead der Partitionierung werden erfasst und dem Designer zur Verfügung gestellt, was die Qualität und Produktivität des weiter erhöht. Die vorgestellten Tools werden mit einer modernen VP für verschiedene SW-Anwendungen evaluiert. Bei Betrachtung des Energieverzögerungsprodukts wurde eine Verringerung der Explorationszeit um mehr als 62% bei 90% Parametergenauigkeit festgestell. Darauf aufbauend, erleichtert die automatisierte Untersuchung verschiedener HW/SW Partitionierungen die Entwicklung heterogener Architekturen durch die Kombination moderner HLS mit Architektur-Exploration auf der Systemebene

Design space exploration for optmized irregular topology networks on chip: the UTNoC

Durante o projeto de arquiteturas multiprocessadas, a etapa de exploração do espaço de projeto pode ser auxiliada por ferramentas que aceleram o processo. O projeto de uma arquitetura com comunicação baseada em rede-em-chip, usualmente considera topologias regulares, e de caráter genérico, desconsiderando uma eventual irregularidade no padrão de comunicação entre os elementos interligados. Projetos heterogêneos necessitam de soluções de comunicação ad-hoc, onde a exploração manual do espaço de projeto se torna inviável, dada a sua complexidade. O presente trabalho propõe uma rede em chip de topologia irregular, capaz de ter bons desempenhos (próximo ao desempenho de uma rede conectada segundo o grafo da aplicação), por meio de um processo de comunicação baseado em tabelas de roteamento. Também, uma ferramenta de exploração em alto nível utilizando Algoritmo Genético, capaz de encontrar redes UTNoCs com número reduzido de conexões, e auxiliando em decisões de projetos destas redes. Resultados obtidos corroboram o trabalho, obtendo redes UTNoCs com desempenhos próximos aos de redes conectadas segundo os grafos de suas aplicações, e com redução no número de conexões de até 54%, representando uma redução significativa de área e consumo de energia.During the design of multiprocessor architectures, the design space exploration step may be aided by tools that assist and accelerate this process. The project of architectures whose communications are based on Networks-on-Chip (NoCs), usually relies on regular topologies, disregarding a possible irregularity in the communication pattern between the interconnected elements. The present work proposes an irregular topology chip network, capable of having good performance (close to the performance of a network connected according to the application graph), through a communication process based on routing tables. The work proposes also a high-level exploration tool using Genetic Algorithm, able to find UTNoC networks with reduced number of connections, and assisting in the design decisions of these networks. The obtained Results show that it’s possible to obtain UTNoC networks with performances close to the performance of networks connected according to the graphs of their applications, and with a reduction in the number of connections of up to 54%, representing a significant reduction of area and energy consumption