Modeling and Design of Digital Electronic Systems

The paper is concerned with the modern methodologies for holistic modeling of electronic systems enabling system-on-chip design. The method deals with the functional modeling of complete electronic systems using the behavioral features of Hardware Description Languages or high level languages then targeting programmable devices - mainly Field Programmable Gate Arrays (FPGAs) - for the rapid prototyping of digital electronic controllers. This approach offers major advantages such as: a unique modeling and evaluation environment for complete power systems, the same environment is used for the rapid prototyping of the digital controller, fast design development, short time to market, a CAD platform independent model, reusability of the model/design, generation of valuable IP, high level hardware/software partitioning of the design is enabled, Concurrent Engineering basic rules (unique EDA environment and common design database) are fulfilled. The recent evolution of such design methodologies is marked through references to case studies of electronic system modeling,simulation, controller design and implementation. Pointers for future trends / evolution of electronic design strategies and tools are given

Taking Intellectual Property Rights Seriously: Are We In or Out? (Phase 1: Intellectual Property Awareness Among Students and Faculty: Tracking Changing Attitudes and Awareness)

The study was conducted to assess the intellectual property awareness among students and faculty was undertaken to determine attitudes, existing IP delivery, drivers seeking information, aspirations, identify unmet needs and generate suggestions to improve the IP system. A mixed method approach using both quantitative and qualitative methodologies were carried out to a prospective group of students and faculty. Data were analyzed and descriptive statistics were used and further analysis using inferential statistics were calculated to compare results. For the students, the most important and relevant topics to the study of Intellectual Property includes knowing where to find and use patent information and the most common method of delivering IP lessons was through briefing workshop on IP, followed by modules and integrating issues in the course. In order to improve IP Delivery, students noted that they prefer to give more emphasis on the overview of IP, patents, copyright, design right and plagiarism. However, students considered that they know some things about Intellectual Property but there were gaps to be filled in. Findings revealed from faculty respondents showed association of the inclusion of the understanding of disclosure and confidentiality to gender, program of students handled by faculty, and cluster where faculty belongs. Moreover, recognition for collaborative work has significant impact on program of students and academic level of faculty. Similarly, other relevant topics like exploiting ideas commercially was found to be associated also with the program of students handled by faculty. Tenure classification was indicated to be associated with understanding health and safety regulations. Results of the focus group discussion with faculty members included improvement of IP delivery and services, curriculum development to include IP education, problems on IP processing, preparation of documents for application. Keywords: intellectual property awareness, IP rights, IP perspectives and insight

Measuring Infringement of Intellectual Property Rights

© Crown Copyright 2014. You may re-use this information (excluding logos) free of charge in any format or medium, under the terms of the Open Government Licence. To view this licence, visit http://www.nationalarchives.gov. uk/doc/open-government-licence/ Where we have identified any third party copyright information you will need to obtain permission from the copyright holders concernedThe review is wide-ranging in scope and overall our findings evidence a lack of appreciation among those producing research for the high-level principles of measurement and assessment of scale. To date, the approaches adopted by industry seem more designed for internal consumption and are usually contingent on particular technologies and/or sector perspectives. Typically, there is a lack of transparency in the methodologies and data used to form the basis of claims, making much of this an unreliable basis for policy formulation. The research approaches we found are characterised by a number of features that can be summarised as a preference for reactive approaches that look to establish snapshots of an important issue at the time of investigation. Most studies are ad hoc in nature and on the whole we found a lack of sustained longitudinal approaches that would develop the appreciation of change. Typically the studies are designed to address specific hypotheses that might serve to support the position of the particular commissioning body. To help bring some structure to this area, we propose a framework for the assessment of the volume of infringement in each different area. The underlying aim is to draw out a common approach wherever possible in each area, rather than being drawn initially to the differences in each field. We advocate on-going survey tracking of the attitudes, perceptions and, where practical, behaviours of both perpetrators and claimants in IP infringement. Clearly, the nature of perpetrators, claimants and enforcement differs within each IPR but in our view the assessment for each IPR should include all of these elements. It is important to clarify that the key element of the survey structure is the adoption of a survey sampling methodology and smaller volumes of representative participation. Once selection is given the appropriate priority, a traditional offline survey will have a part to play, but as the opportunity arises, new technological methodologies, particularly for the voluntary monitoring of online behaviour, can add additional detail to the overall assessment of the scale of activity. This framework can be applied within each of the IP right sectors: copyright, trademarks,patents, and design rights. It may well be that the costs involved with this common approach could be mitigated by a syndicated approach to the survey elements. Indeed, a syndicated approach has a number of advantages in addition to cost. It could be designed to reduce any tendency either to hide inappropriate/illegal activity or alternatively exaggerate its volume to fit with the theme of the survey. It also has the scope to allow for monthly assessments of attitudes rather than being vulnerable to unmeasured seasonal impacts

A Reuse-based framework for the design of analog and mixed-signal ICs

Despite the spectacular breakthroughs of the semiconductor industry, the ability to design integrated circuits (ICs) under stringent time-to-market (TTM) requirements is lagging behind integration capacity, so far keeping pace with still valid Moore's Law. The resulting gap is threatening with slowing down such a phenomenal growth. The design community believes that it is only by means of powerful CAD tools and design methodologies -and, possibly, a design paradigm shift-that this design gap can be bridged. In this sense, reuse-based design is seen as a promising solution, and concepts such as IP Block, Virtual Component, and Design Reuse have become commonplace thanks to the significant advances in the digital arena. Unfortunately, the very nature of analog and mixed-signal (AMS) design has hindered a similar level of consensus and development. This paper presents a framework for the reuse-based design of AMS circuits. The framework is founded on three key elements: (1) a CAD-supported hierarchical design flow that facilitates the incorporation of AMS reusable blocks, reduces the overall design time, and expedites the management of increasing AMS design complexity; (2) a complete, clear definition of the AMS reusable block, structured into three separate facets or views: the behavioral, structural, and layout facets, the two first for top-down electrical synthesis and bottom-up verification, the latter used during bottom-up physical synthesis; (3) the design for reusability set of tools, methods, and guidelines that, relying on intensive parameterization as well as on design knowledge capture and encapsulation, allows to produce fully reusable AMS blocks. A case study and a functional silicon prototype demonstrate the validity of the paper's proposals.Ministerio de Educación y Ciencia TEC2004-0175

BEHAVIOURAL MODELLING FOR THE DESIGN OF HIGH SPEED PHYSICAL LAYERS

This thesis work is the result of a 9 months activity at the IP&Reuse Division - Physical Layer team - of Intel Mobile Communications GmbH in Munich, Germany; the work has been sponsored by the company itself and by an Erasmus grant in the context of ‘LifeLongLearning Program’, academic year 2011-2012. It has been developed a high-level simulation environment to support the concept, architectural exploration and system-level performance analysis of High Speed Serial Interfaces’ Physical Layer. Equivalent representation using Analogue Mixed Signal - Hardware Description Languages (HDLs-AMS) have been also implemented to speed-up full chip transistor-level transient simulations. In Chapter 1 is presented an overview of the state of the art on methodologies, styles, implementation languages and simulation tools used in the design of mixed-signal systems and in the creation of behavioural models. Practical rules for trading off accuracy and speed are also discussed. In Chapter 2, a high-level description of a generic Physical Layer structure is introduced and all the basic building blocks are analyzed; for each of them it has been implemented a model: the realization methodology is presented and discussed in detail. The focus is put on the analysis of the Transmitter, the PCB interconnection, the Receiver, the Phased Locked Loops (PLLs) and the Clock and Data Recovery (CDR). Chapter 3 analyzes the fundamental parameters that determine the performances of a Physical Layer; the construction and the use of the Eye diagram are presented together with the actions to extract timing information and, then, to perform a budget. The various types of jitter and the corresponding causes are discussed. A statistical abstraction is introduced toward the computation of the Bit Error Rate (BER). In Chapter 4, it is illustrated the theory behind a MATLAB script that analyzes the channel pulse response to extract worst-case scenarios and to study the impact of a simple equalizer stage on the overall PHY’s performances; the design key-parameters of this block are then extracted and used in a VHDL-AMS implementation

ChattaBox: A Case Study in Using UML and SDL for Engineering Concurrent Communicating Software Systems

This paper describes a case study that was conducted to investigate software engineering of concurrent communicating systems (CCSs). Best practice software engineering methodologies were used to specify and design a Voice over IP (VoIP) system, which was then implemented. The methodologies utilised were the Unified Modelling Language (UML) and the Specification and Description Language (SDL), and the project specifically explored their combined use. The VoIP system implemented, called ChattaBox, allowed users to communicate via voice, as well as several other features. The system requirements and static design for the system were carried out using UML diagrams. Dynamic design was done using UML initially, followed by a conversion to SDL using a tool provided by Telelogic. The resulting SDL design was verified using the tool. The final system was tested for correctness, performance and usability. It met all of the requirements set out at the initial phase of the engineering process, whilst remaining stable and protocol compliant. After evaluating the engineering process itself, it was concluded that the software engineering paradigm is vital to the field of CCS engineering. Furthermore, UML was useful for providing fast high level design capabilities, but was unable to provide adequate verification of the design. The converted SDL diagrams made up for this, although the biggest drawback of the proposed software engineering process was the inefficient and error-prone conversion, which needed much manual correction and intervention

A case study for NoC based homogeneous MPSoC architectures

The many-core design paradigm requires flexible and modular hardware and software components to provide the required scalability to next-generation on-chip multiprocessor architectures. A multidisciplinary approach is necessary to consider all the interactions between the different components of the design. In this paper, a complete design methodology that tackles at once the aspects of system level modeling, hardware architecture, and programming model has been successfully used for the implementation of a multiprocessor network-on-chip (NoC)-based system, the NoCRay graphic accelerator. The design, based on 16 processors, after prototyping with field-programmable gate array (FPGA), has been laid out in 90-nm technology. Post-layout results show very low power, area, as well as 500 MHz of clock frequency. Results show that an array of small and simple processors outperform a single high-end general purpose processo