289 research outputs found

    Community Partnerships for Cultural Participation: Concepts, Prospects, and Challenges

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    Evaluates the first year of the Wallace Foundation's Community Partnerships for Cultural Participation Initiative, which funded nine community foundations working to increase participation in the arts and culture in their communities

    Delivering competitiveness across management consulting firm and client firm boundaries

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    This study helps frame management consulting theory. It establishes the management consulting firm's networked competencies systems as mechanisms advancing a contracting client firm's operational capabilities, while also optimizting its business deliverables systems. This strategic 'management consulting firm' to 'client firm' relationship focuses into enhancing client firm sustainable (competetive) business positioning

    Towards optical beamforming systems on-chip for millimeter wave wireless communications

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    Towards optical beamforming systems on-chip for millimeter wave wireless communications

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    Memory Subsystem Optimization Techniques for Modern High-Performance General-Purpose Processors

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    abstract: General-purpose processors propel the advances and innovations that are the subject of humanity’s many endeavors. Catering to this demand, chip-multiprocessors (CMPs) and general-purpose graphics processing units (GPGPUs) have seen many high-performance innovations in their architectures. With these advances, the memory subsystem has become the performance- and energy-limiting aspect of CMPs and GPGPUs alike. This dissertation identifies and mitigates the key performance and energy-efficiency bottlenecks in the memory subsystem of general-purpose processors via novel, practical, microarchitecture and system-architecture solutions. Addressing the important Last Level Cache (LLC) management problem in CMPs, I observe that LLC management decisions made in isolation, as in prior proposals, often lead to sub-optimal system performance. I demonstrate that in order to maximize system performance, it is essential to manage the LLCs while being cognizant of its interaction with the system main memory. I propose ReMAP, which reduces the net memory access cost by evicting cache lines that either have no reuse, or have low memory access cost. ReMAP improves the performance of the CMP system by as much as 13%, and by an average of 6.5%. Rather than the LLC, the L1 data cache has a pronounced impact on GPGPU performance by acting as the bandwidth filter for the rest of the memory subsystem. Prior work has shown that the severely constrained data cache capacity in GPGPUs leads to sub-optimal performance. In this thesis, I propose two novel techniques that address the GPGPU data cache capacity problem. I propose ID-Cache that performs effective cache bypassing and cache line size selection to improve cache capacity utilization. Next, I propose LATTE-CC that considers the GPU’s latency tolerance feature and adaptively compresses the data stored in the data cache, thereby increasing its effective capacity. ID-Cache and LATTE-CC are shown to achieve 71% and 19.2% speedup, respectively, over a wide variety of GPGPU applications. Complementing the aforementioned microarchitecture techniques, I identify the need for system architecture innovations to sustain performance scalability of GPG- PUs in the face of slowing Moore’s Law. I propose a novel GPU architecture called the Multi-Chip-Module GPU (MCM-GPU) that integrates multiple GPU modules to form a single logical GPU. With intelligent memory subsystem optimizations tailored for MCM-GPUs, it can achieve within 7% of the performance of a similar but hypothetical monolithic die GPU. Taking a step further, I present an in-depth study of the energy-efficiency characteristics of future MCM-GPUs. I demonstrate that the inherent non-uniform memory access side-effects form the key energy-efficiency bottleneck in the future. In summary, this thesis offers key insights into the performance and energy-efficiency bottlenecks in CMPs and GPGPUs, which can guide future architects towards developing high-performance and energy-efficient general-purpose processors.Dissertation/ThesisDoctoral Dissertation Computer Science 201

    Enhanced decoupling current scheme with selective harmonic elimination pulse width modulation for cascaded multilevel inverter based static synchronous compensator

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    This dissertation is dedicated to a comprehensive study and performance analysis of the transformer-less Multilevel Cascaded H-bridge Inverter (MCHI) based STATic synchronous COMpensator (STATCOM). Among the shunt-connected Flexible AC Transmission System (FACTS) controllers, STATCOM has shown extensive feasibility and effectiveness in solving a wide range of power quality problems. By referring to the literature reviews, MCHI with separated DC capacitors is certainly the most versatile power inverter topology for STATCOM applications. However, due to the ill-defined transfer functions, complex control schemes and formulations were emerged to achieve a low-switching frequency high-bandwidth power control. As a result, adequate controller parameters were generally obtained by using trial and error method, which were practically ineffective and time-consuming. In this dissertation, the STATCOM is controlled to provide reactive power (VAR) compensation at the Point of Common Coupling (PCC) under different loading conditions. The goal of this work is to enhance the performance of the STATCOM with the associated proposed control scheme in achieving high dynamic response, improving transient performance, and producing high-quality output voltage waveform. To evaluate the superiority of the proposed control scheme, intensive simulation studies and numerous experiments are conducted accordingly, where a very good match between the simulation results and the experimental results is achieved in all cases and documented in this dissertation

    Architectural Techniques for Multi-Level Cell Phase Change Memory Based Main Memory

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    Phase change memory (PCM) recently has emerged as a promising technology to meet the fast growing demand for large capacity main memory in modern computing systems. Multi-level cell (MLC) PCM storing multiple bits in a single cell offers high density with low per-byte fabrication cost. However, PCM suffers from long write latency, short cell endurance, limited write throughput and high peak power, which makes it challenging to be integrated in the memory hierarchy. To address the long write latency, I propose write truncation to reduce the number of write iterations with the assistance of an extra error correction code (ECC). I also propose form switch (FS) to reduce the storage overhead of the ECC. By storing highly compressible lines in single level cell (SLC) form, FS improves read latency as well. To attack the short cell endurance and large peak power, I propose elastic RESET (ER) to construct triple-level cell PCM. By reducing RESET energy, ER significantly reduces peak power and prolongs PCM lifetime. To improve the write concurrency, I propose fine-grained write power budgeting (FPB) observing a global power budget and regulates power across write iterations according to the step-down power demand of each iteration. A global charge pump is also integrated onto a DIMM to boost power for hot PCM chips while staying within the global power budget. To further reduce the peak power, I propose intra-write RESET scheduling distributing cell RESET initializations in the whole write operation duration, so that the on-chip charge pump size can also be reduced
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