Device Modeling and Circuit Design of Neuromorphic Memory Structures

The downscaling of CMOS technology and the benefits gleaned thereof have made it the cornerstone of the semiconductor industry for many years. As the technology reaches its fundamental physical limits, however, CMOS is expected to run out of steam instigating the exploration of new nanoelectronic devices. Memristors have emerged as promising candidates for future computing paradigms, specifically, memory arrays and neuromorphic circuits. Towards this end, this dissertation will explore the use of two memristive devices, namely, Transition Metal Oxide (TMO) devices and Insulator Metal Transition (IMT) devices in constructing neuromorphic circuits. A compact model for TMO devices is first proposed and verified against experimental data. The proposed model, unlike most of the other models present in the literature, leverages the instantaneous resistance of the device as the state variable which facilitates parameter extraction. In addition, a model for the forming voltage of TMO devices is developed and verified against experimental data and Monte Carlo simulations. Impact of the device geometry and material characteristics of the TMO device on the forming voltage is investigated and techniques for reducing the forming voltage are proposed. The use of TMOs in syanptic arrays is then explored and a multi-driver write scheme is proposed that improves their performance. The proposed technique enhances voltage delivery across the selected cells via suppressing the effective line resistance and leakage current paths, thus, improving the performance of the crossbar array. An IMT compact model is also developed and verified against experiemntal data and electro-thermal device simulations. The proposed model describes the device as a memristive system with the temperature being the state variable, thus, capturing the temperature dependent resistive switching of the IMT device in a compact form suitable for SPICE implementation. An IMT based Integrate-And-Fire neuron is then proposed. The IMT neuron leverages the temperature dynamics of the device to deliver the functionality of the neuron. The proposed IMT neuron is more compact than its CMOS counterparts as it alleviates the need for complex CMOS circuitry. Impact of the IMT device parameters on the neuron\u27s performance is then studied and design considerations are provided

높은 정류비를 갖는 저항변화 시냅스 소자의 제작 및 스파이킹 뉴럴 네트워크에 미치는 영향 분석

학위논문 (석사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2020. 8. 박병국.This thesis suggests reverse leakage current problem which can occur when resistive random access memory (RRAM) is integrated as synaptic device with integrate-and-fire (IF) neuron circuit in spiking neural network (SNN). To this issue, self-rectifying RRAM was proposed as a solution. Ni/W/SiNx/n-Si RRAM with different bottom electrode (BE) doping concentration was fabricated and measured. Their DC and rectifying characteristics were analyzed based on the measurement data. Among them, self-rectifying RRAM with lowest BE doping concentration exhibited foremost rectifying characteristics without any additional selector or diode device. Furthermore, hardware-based system level simulation was conducted to evaluate the effect of self-rectifying RRAM synapse on spiking neural network. As a result, total 10.2%p of accuracy increment was obtained in MNIST pattern recognition simulation, utilizing the proposed RRAM.본 논문에서는 저항변화메모리가 시냅스 소자로서 스파이킹 뉴럴네트워크에 인테그레이트-앤-파이어 뉴런 회로와 집적될 때에 발생하는 역방향 누설 전류 문제에 대해서 제안한다. 또한, 이러한 문제를 해결하기 위해 자가정류기능이 있는 저항변화메모리를 제안 및 제작하였다. 니켈/텅스텐/실리콘나이트라이드/실리콘 의 구조를 가진 자가정류기능의 저항변화메모리를 하부전극의 도핑 농도를 다르게 하여 제작하였고 측정하였다. 측정결과를 바탕으로 소자들의 전압-전류 특성과 정류 특성을 분석한 결과, 제작한 소자들 중 가장 낮은 도핑 농도의 하부전극을 가진 저항변화메모리의 정류비가 가장 큰 것으로 확인하였다. 나아가 제안하는 자가정류기능의 저항변화메모리가 스파이킹 뉴럴 네트워크에 어떤 영향을 미치는지 확인하기 위하여 하드웨어 기반 시스템 레벨 시뮬레이션을 진행하였다. 그 결과, 자기정류기능의 소자를 시냅스로 한 뉴럴 네트워크에서의 MNIST 패턴 인식 시뮬레이션 인식률이 총 10.2%p 증가 하였다. 본 논문에서 제시하는 자가정류 소자는 이후 다양한 뉴로모픽 어플리케이션의 결과를 성공으로 이끌 수 있는 가능성을 지닌다.Chapter 1. Introduction 1 1.1. Integrate-and-fire Neuron Circuit 3 1.2. Resistive Random Access Memory 5 Chapter 2. Reverse Leakage Current in Neuron Circuit 8 2.1. Reverse Leakage Current 8 Chapter 3. Self-rectifying RRAM 12 3.1. Self-rectifying RRAM 12 3.2. Measurement and Analysis 15 Chapter 4. System Level Evaluation 20 4.1. System Level Evaluation of Self-Rectifying RRAM 20 4.2. Simulation Results 24 Chapter 5. Conclusions 27 References 28 Abstract in Korean 33Maste

Memcapacitive Devices in Logic and Crossbar Applications

Over the last decade, memristive devices have been widely adopted in computing for various conventional and unconventional applications. While the integration density, memory property, and nonlinear characteristics have many benefits, reducing the energy consumption is limited by the resistive nature of the devices. Memcapacitors would address that limitation while still having all the benefits of memristors. Recent work has shown that with adjusted parameters during the fabrication process, a metal-oxide device can indeed exhibit a memcapacitive behavior. We introduce novel memcapacitive logic gates and memcapacitive crossbar classifiers as a proof of concept that such applications can outperform memristor-based architectures. The results illustrate that, compared to memristive logic gates, our memcapacitive gates consume about 7x less power. The memcapacitive crossbar classifier achieves similar classification performance but reduces the power consumption by a factor of about 1,500x for the MNIST dataset and a factor of about 1,000x for the CIFAR-10 dataset compared to a memristive crossbar. Our simulation results demonstrate that memcapacitive devices have great potential for both Boolean logic and analog low-power applications

Vertical III-V Nanowires For In-Memory Computing

In recent times, deep neural networks (DNNs) have demonstrated great potential in various machine learning applications,such as image classification and object detection for autonomous driving. However, increasing the accuracy of DNNsrequires scaled, faster, and more energy-efficient hardware, which is limited by the von Neumann architecture whereseparate memory and computing units lead to a bottleneck in performance. A promising solution to address the vonNeumann bottleneck is in-memory computing, which can be achieved by integrating non-volatile memory cells such asRRAMs into dense crossbar arrays. On the hardware side, the 1-transistor-1-resistor (1T1R) configuration has been centralto numerous demonstrations of reservoir, in-memory and neuromorphic computing.In this thesis, to achieve a 1T1R cell with a minimal footprint of 4F2, a technology platform has been developed to integrate avertical nanowire GAA MOSFET as a selector device for the RRAM. Firstly, the effect of the geometry (planar to vertical) ofthe ITO/HfO2/TiN RRAM cell was studied where low energy switching (0.49 pJ) and high endurance (106) were achievedin the vertical configuration. Furthermore, InAs was incorporated as the GAA MOSFET selector channel material toleverage the beneficial transport properties of III-V materials desirable for supply voltage scaling. Finally, an approach wasdeveloped wherein InAs is used as the selector channel as well as the RRAM electrode by carefully tuning the InAs nativeoxides. This thesis also presents low-frequency noise characterization of the RRAM cell as well as the MOSFET to furtherunderstand the semiconductor/oxide interface. The vertical 1T1R cell developed in this thesis enables the implementationof Boolean logic operations using a single vertical nanowire while reducing the footprint by 51x when compared to itstraditional CMOS counterpart

Design of Resistive Synaptic Devices and Array Architectures for Neuromorphic Computing

abstract: Over the past few decades, the silicon complementary-metal-oxide-semiconductor (CMOS) technology has been greatly scaled down to achieve higher performance, density and lower power consumption. As the device dimension is approaching its fundamental physical limit, there is an increasing demand for exploration of emerging devices with distinct operating principles from conventional CMOS. In recent years, many efforts have been devoted in the research of next-generation emerging non-volatile memory (eNVM) technologies, such as resistive random access memory (RRAM) and phase change memory (PCM), to replace conventional digital memories (e.g. SRAM) for implementation of synapses in large-scale neuromorphic computing systems. Essentially being compact and “analog”, these eNVM devices in a crossbar array can compute vector-matrix multiplication in parallel, significantly speeding up the machine/deep learning algorithms. However, non-ideal eNVM device and array properties may hamper the learning accuracy. To quantify their impact, the sparse coding algorithm was used as a starting point, where the strategies to remedy the accuracy loss were proposed, and the circuit-level design trade-offs were also analyzed. At architecture level, the parallel “pseudo-crossbar” array to prevent the write disturbance issue was presented. The peripheral circuits to support various parallel array architectures were also designed. One key component is the read circuit that employs the principle of integrate-and-fire neuron model to convert the analog column current to digital output. However, the read circuit is not area-efficient, which was proposed to be replaced with a compact two-terminal oscillation neuron device that exhibits metal-insulator-transition phenomenon. To facilitate the design exploration, a circuit-level macro simulator “NeuroSim” was developed in C++ to estimate the area, latency, energy and leakage power of various neuromorphic architectures. NeuroSim provides a wide variety of design options at the circuit/device level. NeuroSim can be used alone or as a supporting module to provide circuit-level performance estimation in neural network algorithms. A 2-layer multilayer perceptron (MLP) simulator with integration of NeuroSim was demonstrated to evaluate both the learning accuracy and circuit-level performance metrics for the online learning and offline classification, as well as to study the impact of eNVM reliability issues such as data retention and write endurance on the learning performance.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Neuromorphic computing using non-volatile memory

Dense crossbar arrays of non-volatile memory (NVM) devices represent one possible path for implementing massively-parallel and highly energy-efficient neuromorphic computing systems. We first review recent advances in the application of NVM devices to three computing paradigms: spiking neural networks (SNNs), deep neural networks (DNNs), and ‘Memcomputing’. In SNNs, NVM synaptic connections are updated by a local learning rule such as spike-timing-dependent-plasticity, a computational approach directly inspired by biology. For DNNs, NVM arrays can represent matrices of synaptic weights, implementing the matrix–vector multiplication needed for algorithms such as backpropagation in an analog yet massively-parallel fashion. This approach could provide significant improvements in power and speed compared to GPU-based DNN training, for applications of commercial significance. We then survey recent research in which different types of NVM devices – including phase change memory, conductive-bridging RAM, filamentary and non-filamentary RRAM, and other NVMs – have been proposed, either as a synapse or as a neuron, for use within a neuromorphic computing application. The relevant virtues and limitations of these devices are assessed, in terms of properties such as conductance dynamic range, (non)linearity and (a)symmetry of conductance response, retention, endurance, required switching power, and device variability.11Yscopu