Miniaturized Low-Voltage Power Converters With Fast Dynamic Response

This paper demonstrates a two-stage approach for power conversion that combines the strengths of variable-topology switched capacitor techniques (small size and light-load performance) with the regulation capability of magnetic switch-mode power converters. The proposed approach takes advantage of the characteristics of complementary metal-oxide-semiconductor (CMOS) processes, and the resulting designs provide excellent efficiency and power density for low-voltage power conversion. These power converters can provide low-voltage outputs over a wide input voltage range with very fast dynamic response. Both design and fabrication considerations for highly integrated CMOS power converters using this architecture are addressed. The results are demonstrated in a 2.4-W dc-dc converter implemented in a 180-nm CMOS IC process and co-packaged with its passive components for high performance. The power converter operates from an input voltage of 2.7-5.5 V with an output voltage of ≤1.2 V, and achieves a 2210 W/in[superscript 3] power density with ≥80% efficiency.Focus Center Research ProgramUnited States. Defense Advanced Research Projects AgencySemiconductor Research CorporationCharles Stark Draper Laborator

The road to fully integrated DC-DC conversion via the switched-capacitor approach

This paper provides a perspective on progress toward realization of efficient, fully integrated dc-dc conversion and regulation functionality in CMOS platforms. In providing a comparative assessment between the inductor-based and switched-capacitor approaches, the presentation reviews the salient features in effectiveness in utilization of switch technology and in use and implementation of passives. The analytical conclusions point toward the strong advantages of the switched-capacitor (SC) approach with respect to both switch utilization and much higher energy densities of capacitors versus inductors. The analysis is substantiated with a review of recently developed and published integrated dc-dc converters of both the inductor-based and SC types. © 2012 IEEE

Power Converters and Power Quality

This paper discusses the subject of power quality for power converters. The first part gives an overview of most of the common disturbances and power quality issues in electrical networks for particle accelerators, and explains their consequences for accelerator operation. The propagation of asymmetrical network disturbances into a network is analysed. Quantitative parameters for network disturbances in a typical network are presented, and immunity levels for users' electrical equipment are proposed. The second part of this paper discusses the technologies and strategies used in particle accelerator networks for power quality improvement. Particular focus is given to networks supplying loads with cycling active and reactive power.Comment: 26 pages, contribution to the 2014 CAS - CERN Accelerator School: Power Converters, Baden, Switzerland, 7-14 May 201

Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm

A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently constraint the converter design space. This algorithm precludes the cost of lengthy bottom-up verifications and speeds up the synthesis task. The approach is herein demonstrated via the design of a 0.13 μm CMOS 10 bits@60 MS/s pipeline ADC with energy consumption per conversion of only 0.54 pJ@1 MHz, making it one of the most energy-efficient 10-bit video-rate pipeline ADCs reported to date. The computational cost of this design is of only 25 min of CPU time, and includes the evaluation of 13 different pipeline architectures potentially feasible for the targeted specifications. The optimum design derived from the synthesis procedure has been fine tuned to support PVT variations, laid out together with other auxiliary blocks, and fabricated. The experimental results show a power consumption of 23 [email protected] V and an effective resolution of 9.47-bit@1 MHz. Bearing in mind that no specific power reduction strategy has been applied; the mentioned results confirm the reliability of the proposed approach.Ministerio de Ciencia e Innovación TEC2009-08447Junta de Andalucía TIC-0281

Experimental Test bed to De-Risk the Navy Advanced Development Model

This paper presents a reduced scale demonstration test-bed at the University of Texas’ Center for Electromechanics (UT-CEM) which is well equipped to support the development and assessment of the anticipated Navy Advanced Development Model (ADM). The subscale ADM test bed builds on collaborative power management experiments conducted as part of the Swampworks Program under the US/UK Project Arrangement as well as non-military applications. The system includes the required variety of sources, loads, and controllers as well as an Opal-RT digital simulator. The test bed architecture is described and the range of investigations that can be carried out on it is highlighted; results of preliminary system simulations and some initial tests are also provided. Subscale ADM experiments conducted on the UT-CEM microgrid can be an important step in the realization of a full-voltage, full-power ADM three-zone demonstrator, providing a test-bed for components, subsystems, controls, and the overall performance of the Medium Voltage Direct Current (MVDC) ship architecture.Center for Electromechanic

Voltage regulation considerations for the design of hybrid distribution transformers

The future substation depends on finding a way to mitigate the effects of the drawbacks of the conventional legacy by employing the efficiency of the solid state switches [1]. This paper discusses the considerations of designing a distribution transformer that provides additional functions in regulating the voltage and controlling the reactive power that is injected in the distribution network, using a fractional rated converter attached partially with the windings of the transformer. This approach aims mainly to enhance the unit with more flexibility in controlling the voltage at the last mile of the network, in order to decrease the losses and meet the future expectations for low voltage networks modifications, and that by using a power electronic (PE) approach has less losses and more functionality (depending on the reliability of transformer and intelligence of PE). The design of a hybrid distribution transformer is detailed and its functionality in regulating the voltage is discussed as a combination between the features of one of the most reliable network devices, the transformer, and the effect of PE existence with less losses in both switching and conduction losses. Reduced ratings PE are used in this approach, whereby the solid state switches are controlled according to the immediate need for voltage control in low voltage (LV) networks

STUDY OF FULLY-INTEGRATED LOW-DROPOUT REGULATORS

Department of Electrical EngineeringThis thesis focuses on the introduction of fully-integrated low-dropout regulators (LDOs). Recently, for the mobile and internet-of-things applications, the level of integration is getting higher. LDOs get popular in integrated circuit design including functions such as reducing switching ripples from high-efficiency regulators, cancelling spurs from other loads, and giving different supply voltages to loads. In accordance with load applications, choosing proper LDOs is important. LDOs can be classified by the types of power MOSEFT, the topologies of error amplifier, and the locations of dominant pole. Analog loads such as voltage-controlled oscillators and analog-to-digital converters need LDOs that have high power-supply-rejection-ratio (PSRR), high accuracy, and low noise. Digital loads such as DRAM and CPU need fast transient response, a wide range of load current providable LDOs. As an example, we present the design procedure of a fully-integrated LDO that obtains the desired PSRR. In analog LDOs, we discuss advanced techniques such as local positive feedback loop and zero path that can improve stability and PSRR performance. In digital LDOs, the techniques to improve transient response are introduced. In analog-digital hybrid LDOs, to achieve both fast transient and high PSRR performance in a fully-integrated chip, how to optimally combine analog and digital LDOs is considered based on the characteristics of each LDO type. The future work is extracted from the considerations and limitations of conventional techniques.clos

A Multiproject Chip Approach to the Teaching of Analog MOS LSI and VLSI

Multiproject chip implementation has been used in teaching analog MOS circuit design. After having worked with computer simulation and layout aids in homework problems, students designed novel circuits including several high performance op amps, an A/D converter, a switched capacitor filter, a 1 K dynamic RAM, and a variety of less conventional MOS circuits such as a VII converter, an AC/DC converter, an AM radio receiver, a digitally-controlled analog signal processor, and on-chip circuitry for measuring transistor capacitances. These circuits were laid out as part of an NMOS multiproject chip. Several of the designs exhibit a considerable degree of innovation; fabrication pending, computer simulation shows that some may be pushing the state of the art. Several designs are of interest to digital designers; in fact, the course has provided knowledge and technique needed for detailed digital circuit design at the gate level

Multilevel single phase isolated inverter with reduced number of switches

This paper proposes a cascaded single phase multilevel inverter using an off-the-shelf three-phase inverter and transformer. The concept is based on a cascaded connection of two inverter legs using a typical three phase inverter in such a way that the third leg is shared between the other two phases. The cascaded connection is achieved through an integrated series transformer with a typical three-phase transformer core. Utilization of a special transformer design has been previously proposed in the Custom Power Active Transformer. However, cascaded connection of inverter legs has not been previously investigated with such a concept. In this way, a three-leg inverter and a three-phase transformer are converted into an isolated multilevel single-phase inverter based on an unique configuration and modulation technique.Postprint (author's final draft