Design and multiplierless realization of digital synthesis filters for hybrid-filter-bank A/D converters

This paper studies the optimal least squares and minimax design and realization of digital synthesis filters for hybrid-filter-bank analog-to-digltal converters (HFB ADCs) to meet a given spurious-free dynamic range (SFDR). The problem for designing finite-impulse-response synthesis filters is formulated as a second-order cone-programming problem, which is convex and allows linear and quadratic constraints such as peak aliasing error to be incorporated. The fixed coefficients of the designed synthesis filters are efficiently implemented using sum-of-power-of-two (SOPOT) coefficients, while the internal word length used for each intermediate data is minimized using geometric programming. The main sources of error are analyzed, and a new formula of SFDR in terms of these errors is derived. The effects of component variations of analog analysis filters on the HFB ADC are also addressed by means of two new robust HFB ADC design algorithms based on stochastic uncertainty and worst case uncertainty models. Design results show that the proposed approach offers more flexibility and better performance than conventional methods in achieving a given SFDR and that the robust design algorithms are more robust to parameter uncertainties than the nominal design in which the uncertainties are not taken into account. © 2009 IEEE.published_or_final_versio

Sensitivity of hybrid filter banks A/D converters to analog realization errors and finite word length

This paper studies the sensitivity of hybrid filter banks (HFB) to analog inaccuracies and finite word implementation. It is shown that very small errors affecting very simple analog structures have a dramatic influence on the performances of the HFB. The influence of the quantization of digital filter coefficients is also studied. A theoretical limit for the error introduced by the quantization of digital filter coefficients is derived

Efficient TV white space filter bank transceiver

Future devices operating in the TV white space (TVWS) spectrum will require to access different bands at different locations and times in order to avoid interference to incumbent users, requiring agility and sufficient spectral masks to satisfy regulators. Further, with very high-speed ADCs and DACs becoming reality, the purpose of this paper is to present a transceiver front-end capable of simultaneously up- and downconverting a significant portion of the UHF band. The proposed approach takes a two-stage filter-bank conversion for implementation on state-of-the-art FPGAs. We present three different parameterisations, which are compatible with the 40 TVWS channels between 470 and 790MHz in Europe, and compare them in terms of complexity and latency

Use of frequency response masking technique in designing A/D converter for SDR.

Thesis (M.Sc.Eng.)-University of KwaZulu-Natal, Durban, 2005.Analog-to-digital converters (ADCs) are required in almost all signal processing and communication systems. They are often the most critical components, since they tend to determine the overall system performance. Hence, it is important to determine their performance limitations and develop improved realizations. One of the most challenging tasks for realizing software defined radio (SDR) is to move ND conversion as close to the antenna as possible, this implies that the ADC has to sample the incoming signal with a very high sample rate (over 100 MSample/s) and with a very high resolution (14 -to -16 bits). To design and implement AID converters with such high performance, it is necessary to investigate new designing techniques. The focus in this work is on a particular type of potentially high-performance (high-resolution and highspeed) analog-to-digital conversion technique, utilizing filter banks, where two or more ADCs are used in the converter array in parallel together with asymmetric filter banks. The hybrid filter bank analog-todigital converter (HFB ADC) utilizes analog filters (analysis filters) to allocate a frequency band to each ADC in a converter array and digital synthesis filters to reconstruct the digitized signal. The HFB improves the speed and resolution of the conversion, in comparison to the standard time-interleaving technique by attenuating the effect of gain and phase mismatches between the ADCs. Many of the designs available in the literature are compromising between some metrics: design complexity, order of the filter bank (computation time) and the sharpness of the frequency response rolloff (the transition from the pass band to the stop band). In this dissertation, five different classes of near perfect magnitude reconstruction (NPMR) continuoustime hybrid filter banks (CT HFBs) are proposed. In each of the five cases, two filter banks are designed; analysis filter bank and synthesis filter bank. Since the systems are hybrid, continuous time IlR filter are used to implement the analysis filter bank and digital filters are used for the synthesis filter bank. To optimize the system, we used a new technique, known in the literature as frequency response masking (FRM), to design the synthesis filter bank. In this technique, the sharp roll-off characteristics can be achieved while keeping the complexity of the filter within practical range, this is done by splitting the filter into two filters in cascade; model filter with relaxed roll-off characteristics followed by a masking filter. One of the main factors controlling the overall complexity of the filter is the way of designing the model filter and that of designing the masking filter. The dissertation proposes three combinations: use of HR model filter and IlR masking filter, HR model filter/FIR masking filter and FIR model filter/FIR masking filter. To show the advantages of our designs, we considered the cases of designing the synthesis filter as one filter, either FIR or IlR. These two filters are used as base for comparison with our proposed designs (the use of masking response filter). The results showed the following: 1. Asymmetric hybrid filter banks alone are not sufficient for filters with sharp frequency response roll-off especially for HR/FIR class. 2. All classes that utilize FRM in their synthesis filter banks gave a good performance in general in comparison to conventional classes, such as the reduction of the order of filters 3. HR/HR FRM gave better performance than HR/FIR FRM. 4. Comparing HR/HR FRM using FIR masking filters and HR/IIR FRM using IIR masking filters, the latter gave better performance (the performance is generally measured in terms of reduced filter order). 5. All classes that use the FRM approach have a very low complexity, in terms of reduced filter order. Our target was to design a system with the following overall characteristics: pass band ripple of -0.01 dB, stop band minimum attenuation of - 40 dB and of response roll-off of 0.002. Our calculations showed that the order of the conventional IIR/FIR filter that achieves such characteristics is aboutN =2000. Using the FRM technique, the order N reduced to aboutN = 244, N = 179 for IIRJFIR and IIR/IIR classes, respectively. This shows that the technique is very effective in reducing the filter complexity. 6. The magnitude distortion and the aliasing noise are calculated for each design proposal and compared with the theoretical values. The comparisons show that all our proposals result in approximately perfect magnitude reconstruction (NPMR). In conclusion, our proposal of using frequency-response masking technique to design the synthesis filter bank can, to large extent, reduce the complexity of the system. The design of the system as a whole is simplified by designing the synthesis filter bank separately from the design of the analysis filter bank. In this case each bank is optimized separately. This implies that for SDR applications we are proposing the use of the continuous-time HFB ADC (CT HFB ADC) structure utilizing FRM for digital filters

Frontend em tempo real para cognitive radio inspirado na cóclea humana

Mestrado em Engenharia Electrónica e TelecomunicaçõesNesta tese vamos discutir a implementação e desenvolvimento de um frontend inspirado na cóclea humana que é capaz de amostrar sinais RF com uma larga largura de banda e gama dinâmica. Este front-end usa um multiplexer de RF de 8 canais amostrado por uma placa com 8 ADCs a funcionar a 250MSPS. Uma placa de desenvolvimento com uma FPGA controla a ADC e implementa os ltros de síntese digitais e liga a um computador pessoal para transferir toda a informação e mudar os coe cientes dos ltros em tempo real.In this thesis it will be discussed the real time implementation and development of a front-end inspired by the Human Cochlea that is able to sample RF signals with a large bandwidth and dynamic range. This front-end uses an 8 channel RF multiplexer sampled by an 8 channel 250MSPS ADC board. A FPGA board controls the ADC, implements the digital synthesis lter bank and connects to a personal computer to transfer the data and to change the lters in real-time

Frequency Translation loops for RF filtering-Theory and Design

Modern wireless transceivers are required to operate over a wide range of frequencies in order to support the multitude of currently available wireless standards. Wideband operation also enables future systems that aim for better utilization of the available spectrum through dynamic allocation. As such, co-existence problems like harmonic mixing and phase noise become a main concern. In particular, dealing with interfer- ence scenarios is crucial since they directly translate to higher linearity requirements in a receiver. With CMOS driving the consumer electronics market due to low cost and high level of integration demands, the continued increase in speed, mainly intended for digital applications, oers new possibilities for RF design to improve the linearity of front-end receivers. Furthermore, the readily available switches in CMOS have proven to be a viable alternative to traditional active mixers for frequency translation due to their high linearity, low flicker noise, and, most recently recognized, their impedance transformation properties. In this thesis, frequency translation feedback loops employing passive mixers are explored as a means to relax the linearity requirements in a front-end receiver by providing channel selectivity as early as possible in the receiver chain. The proposed receiver architecture employing such loop addresses some of the most common prob- lems of integrated RF lters, while maintaining their inherent tunability. Through a simplied and intuitive analysis, the operation of the receiver is first examined and the design parameters aecting the lter characteristics, such as band- width and stop-band rejection, are determined. A systematic procedure for analyzing the linearity of the receiver reveals the possibility of LNA distortion canceling, which decouples the trade-o between noise, linearity and harmonic radiation. Next, a detailed analysis of frequency translation loops using passive mixers is developed. Only highly simplied analysis of such loops is commonly available in literature. The analysis is based on an iterative procedure to address the complexity introduced by the presence of LO harmonics in the loop and the lack of reverse isolation in the mixers, and results in highly accurate expressions for the harmonic and noise transfer functions of the system. Compared to the alternative of applying general LPTV theory, the procedure developed oers more intuition into the operation of the system and only requires the knowledge of basic Fourier analysis. The solution is shown to be capable of predicting trade-os arising due to harmonic mixing and loop stability requirements, and is therefore useful for both system design and optimization. Finally, as a proof of concept, a chip prototype is designed in a standard 65nm CMOS process. The design occupies +12dBm. As such, the work presented in this thesis aims to provide a highly-integrated means for programmable RF channel selection in wideband receivers. The topic oers several possibilities for further research, either in terms of extending the viability of the system, for example by providing higher order ltering, or by improving performance, such as noise

Analog baseband circuits for sensor systems

This thesis is composed of six publications and an overview of the research topic, which also summarizes the work. The research presented in this thesis focuses on research into analog baseband circuits for sensor systems. The research is divided into three different topics: the integration of analog baseband circuits into a radio receiver for sensor applications; the integration of an ΔΣ modulator A/D converter into a GSM/WCDMA radio receiver for mobile phones, and the integration of algorithmic A/D converters for a capacitive micro-accelerometer interface. All the circuits are implemented using deep sub-micron CMOS technologies. The work summarizes the design of different blocks for sensor systems. The research into integrated analog baseband circuits for a radio receiver focuses on a circuit structures with a very low power dissipation and that can be implemented using only standard CMOS technologies. The research into integrated ΔΣ modulator A/D converter design for a GSM/WCDMA radio receiver for mobile phones focuses on the implications for analog circuit design emerging from using a very deep sub-micron CMOS process. Finally, in the research into algorithmic A/D converters for a capacitive microaccelerometer interface, new ways of achieving a good performance with low power dissipation, while also minimizing the silicon area of the integrated A/D converter are introduced

Proceedings of the Scientific-Practical Conference "Research and Development - 2016"

talent management; sensor arrays; automatic speech recognition; dry separation technology; oil production; oil waste; laser technolog