Sistema de predicción epileptogenica en lazo cerrado basado en matrices sub-durales

The human brain is the most complex organ in the human body, which consists of approximately 100 billion neurons. These cells effortlessly communicate over multiple hemispheres to deliver our everyday sensorimotor and cognitive abilities. Although the underlying principles of neuronal communication are not well understood, there is evidence to suggest precise synchronisation and/or de-synchronisation of neuronal clusters could play an important role. Furthermore, new evidence suggests that these patterns of synchronisation could be used as an identifier for the detection of a variety of neurological disorders including, Alzheimers (AD), Schizophrenia (SZ) and Epilepsy (EP), where neural degradation or hyper synchronous networks have been detected. Over the years many different techniques have been proposed for the detection of synchronisation patterns, in the form of spectral analysis, transform approaches and statistical based studies. Nonetheless, most are confined to software based implementations as opposed to hardware realisations due to their complexity. Furthermore, the few hardware implementations which do exist, suffer from a lack of scalability, in terms of brain area coverage, throughput and power consumption. Here we introduce the design and implementation of a hardware efficient algorithm, named Delay Difference Analysis (DDA), for the identification of patient specific synchronisation patterns. The design is remarkably hardware friendly when compared with other algorithms. In fact, we can reduce hardware requirements by as much as 80% and power consumption as much as 90%, when compared with the most common techniques. In terms of absolute sensitivity the DDA produces an average sensitivity of more than 80% for a false positive rate of 0.75 FP/h and indeed up to a maximum of 90% for confidence levels of 95%. This thesis presents two integer-based digital processors for the calculation of phase synchronisation between neural signals. It is based on the measurement of time periods between two consecutive minima. The simplicity of the approach allows for the use of elementary digital blocks, such as registers, counters or adders. In fact, the first introduced processor was fabricated in a 0.18μm CMOS process and only occupies 0.05mm2 and consumes 15nW from a 0.5V supply voltage at a signal input rate of 1024S/s. These low-area and low-power features make the proposed circuit a valuable computing element in closed-loop neural prosthesis for the treatment of neural disorders, such as epilepsy, or for measuring functional connectivity maps between different recording sites in the brain. A second VLSI implementation was designed and integrated as a mass integrated 16-channel design. Incorporated into the design were 16 individual synchronisation processors (15 on-line processors and 1 test processor) each with a dedicated training and calculation module, used to build a specialised epileptic detection system based on patient specific synchrony thresholds. Each of the main processors are capable of calculating the phase synchrony between 9 independent electroencephalography (EEG) signals over 8 epochs of time totalling 120 EEG combinations. Remarkably, the entire circuit occupies a total area of only 3.64 mm2. This design was implemented with a multi-purpose focus in mind. Firstly, as a clinical aid to help physicians detect pathological brain states, where the small area would allow the patient to wear the device for home trials. Moreover, the small power consumption would allow to run from standard batteries for long periods. The trials could produce important patient specific information which could be processed using mathematical tools such as graph theory. Secondly, the design was focused towards the use as an in-vivo device to detect phase synchrony in real time for patients who suffer with such neurological disorders as EP, which need constant monitoring and feedback. In future developments this synchronisation device would make an good contribution to a full system on chip device for detection and stimulation.El cerebro humano es el órgano más complejo del cuerpo humano, que consta de aproximadamente 100 mil millones de neuronas. Estas células se comunican sin esfuerzo a través de ambos hemisferios para favorecer nuestras habilidades sensoriales y cognitivas diarias. Si bien los principios subyacentes de la comunicación neuronal no se comprenden bien, existen pruebas que sugieren que la sincronización precisa y/o la desincronización de los grupos neuronales podrían desempeñar un papel importante. Además, nuevas evidencias sugieren que estos patrones de sincronización podrían usarse como un identificador para la detección de una gran variedad de trastornos neurológicos incluyendo la enfermedad de Alzheimer(AD), la esquizofrenia(SZ) y la epilepsia(EP), donde se ha detectado la degradación neural o las redes hiper sincrónicas. A lo largo de los años, se han propuesto muchas técnicas diferentes para la detección de patrones de sincronización en forma de análisis espectral, enfoques de transformación y análisis estadísticos. No obstante, la mayoría se limita a implementaciones basadas en software en lugar de realizaciones de hardware debido a su complejidad. Además, las pocas implementaciones de hardware que existen, sufren una falta de escalabilidad, en términos de cobertura del área del cerebro, rendimiento y consumo de energía. Aquí presentamos el diseño y la implementación de un algoritmo eficiente de hardware llamado “Delay Difference Aproximation” (DDA) para la identificación de patrones de sincronización específicos del paciente. El diseño es notablemente compatible con el hardware en comparación con otros algoritmos. De hecho, podemos reducir los requisitos de hardware hasta en un 80% y el consumo de energía hasta en un 90%, en comparación con las técnicas más comunes. En términos de sensibilidad absoluta, la DDA produce una sensibilidad promedio de más del 80% para una tasa de falsos positivos de 0,75 PF / hr y hasta un máximo del 90% para niveles de confianza del 95%. Esta tesis presenta dos procesadores digitales para el cálculo de la sincronización de fase entre señales neuronales. Se basa en la medición de los períodos de tiempo entre dos mínimos consecutivos. La simplicidad del enfoque permite el uso de bloques digitales elementales, como registros, contadores o sumadores. De hecho, el primer procesador introducido se fabricó en un proceso CMOS de 0.18μm y solo ocupa 0.05mm2 y consume 15nW de un voltaje de suministro de 0.5V a una tasa de entrada de señal de 1024S/s Estas características de baja área y baja potencia hacen que el procesador propuesto sea un valioso elemento informático en prótesis neurales de circuito cerrado para el tratamiento de trastornos neuronales, como la epilepsia, o para medir mapas de conectividad funcional entre diferentes sitios de registro en el cerebro. Además, se diseñó una segunda implementación VLSI que se integró como un diseño de 16 canales integrado en masa. Se incorporaron al diseño 16 procesadores de sincronización individuales (15 procesadores en línea y 1 procesador de prueba), cada uno con un módulo de entrenamiento y cálculo dedicado, utilizado para construir un sistema de detección epiléptico especializado basado en umbrales de sincronía específicos del paciente. Cada uno de los procesadores principales es capaz de calcular la sincronización de fase entre 9 señales de electroencefalografía (EEG) independientes en 8 épocas de tiempo que totalizan 120 combinaciones de EEG. Cabe destacar que todo el circuito ocupa un área total de solo 3.64 mm2. Este diseño fue implementado teniendo en mente varios propósitos. En primer lugar, como ayuda clínica para ayudar a los médicos a detectar estados cerebrales patológicos, donde el área pequeña permitiría al paciente usar el dispositivo para las pruebas caseras. Además, el pequeño consumo de energía permitiría una carga cero del dispositivo, lo que le permitiría funcionar con baterías estándar durante largos períodos. Los ensayos podrían producir información importante específica para el paciente que podría procesarse utilizando herramientas matemáticas como la teoría de grafos. En segundo lugar, el diseño se centró en el uso como un dispositivo in-vivo para detectar la sincronización de fase en tiempo real para pacientes que sufren trastornos neurológicos como el EP, que necesitan supervisión y retroalimentación constantes. En desarrollos futuros, este dispositivo de sincronización sería una buena base para desarrollar un sistema completo de un dispositivo chip para detección de trastornos neurológicos

Simulation and Modeling of Silicon Based Emerging Nanodevices: From Device to Circuit Level

Nanostructure based devices are very promising candidates for the emerging nanotechnologies with advantage in terms of power consumption and functional density. Nanowire Field Effect Transistor (NWFET) and Single Electron Transistor (SET) are the focus of this work. The serious challenges faced by the MOSFET due to scaling limits can be solved by these devices. NWFET provides better gate control and overcomes the short channel effects. SET operates in the quantum confinement regime where the basic operation of MOSFET becomes a challenge. SET works better when the dimensions are small encouraging the process of scaling down. Because of these characteristics of the nanodevices, they have achieved a huge interest from the viewpoint of theoretical as well as applied electronics. The studies focus on the understanding of the basic transport characteristics of the devices. The necessity is to develop a model which is efficient, can be used at circuit level and also provides physical insights of the device. The first part of this work focuses on developing the model for SET and to implement it at the circuit level. The transport properties of SET are studied through quantum simulations. The behavioral characterization of the device is performed and the effect of different device parameters on the transport is studied. Furthermore, the impact of gate voltage is analyzed which modulates the current by shifting the energy levels of the device. After observing the transport through SET, a model is developed that efficiently evaluates the IV characteristics of the device. The quantum simulations are used as reference and a huge computational over-head is achieved while maintaining accuracy. Then the model is implemented in hardware descriptive language showing its functional variability at circuit level by designing some logic circuits like AND, OR and FA. In the second part, the performance of the nanoarrays based on NWFET is characterized. A device level model is developed to evaluate the gate capacitance and drain current of NWFET. Starting from the output of the model, in-house simulator is modified and used to evaluate the switching activity of the devices in nanoarray. A nanoarray implementation for bio-sequence alignment based on a systolic array is realized and its essential performance is evaluated. The power consumption, area and performance of the nanoarray implementation are compared with CMOS implementation. A wide solution space can be explored to find the optimal solution trading power and performance and considering the technological limitations of a realistic implementation

A high performance ASIC for electrical and neurochemical traumatic brain injury monitoring

Traumatic Brain Injury (TBI) can be defined as a non-degenerative, non-congenital brain trauma due to an external mechanical force. TBI is a major cause of death and disability in all age groups and the leading cause of death and disability in working people and among young adults. This Thesis presents the first application specific integrated chip (ASIC) for monitoring patients suffering from TBI. The microelectronic chip was designed to meet the demands of processing physiological signals for an alternative method of TBI monitoring. It has been studied that by monitoring electrical (ECoG) and chemical (glucose, lactate and potassium) signals, the report of spreading depolarisation (SD) waves could be a good indicator for an upcoming secondary brain injury. The ultimate aim of this Thesis has been to support the idea of a “behind-the-ear” micro-platform, which could enable the monitoring of mobile (or mobilized) patients suffering a TBI who, currently, are not monitored. Switched-capacitor (SC) circuits have been adopted for the implementation of both current and voltage analogue front-ends (AFEs). Advanced techniques to minimise noise and improve the noise performance of the circuit were employed. Moreover, a digitally enabled automatic transimpedance gain control circuit, suitable for current analogue front-ends, was developed and tested in order to provide an automated way to adjust the gain and to counterbalance for the drop in sensitivity of the biosensors due to drift. Measured results confirming the operation of the TBI ASIC and its sub-circuits are reported. Finally, a novel circuit that mimics the Butler-Volmer dynamics is presented. The basic building blocks arise from the combination of Translinear (TL) Circuits and the Non- linear Bernoulli Cell Formalism (NBCF). The developed electrical equivalent circuit has been compared to an ideal model, which was developed in MATLAB. The robustness of the microelectronic system was evaluated by means of Monte Carlo simulations.Open Acces

Utilisation des nano-composants électroniques dans les architectures de traitement associées aux imageurs

By using learning mechanisms extracted from recent discoveries in neuroscience, spiking neural networks have demonstrated their ability to efficiently analyze the large amount of data from our environment. The implementation of such circuits on conventional processors does not allow the efficient exploitation of their parallelism. The use of digital memory to implement the synaptic weight does not allow the parallel reading or the parallel programming of the synapses and it is limited by the bandwidth of the connection between the memory and the processing unit. Emergent memristive memory technologies could allow implementing this parallelism directly in the heart of the memory.In this thesis, we consider the development of an embedded spiking neural network based on emerging memory devices. First, we analyze a spiking network to optimize its different components: the neuron, the synapse and the STDP learning mechanism for digital implementation. Then, we consider implementing the synaptic memory with emergent memristive devices. Finally, we present the development of a neuromorphic chip co-integrating CMOS neurons with CBRAM synapses.En utilisant les méthodes d’apprentissages tirées des récentes découvertes en neuroscience, les réseaux de neurones impulsionnels ont démontrés leurs capacités à analyser efficacement les grandes quantités d’informations provenant de notre environnement. L’implémentation de ces circuits à l’aide de processeurs classiques ne permet pas d’exploiter efficacement leur parallélisme. L’utilisation de mémoire numérique pour implémenter les poids synaptique ne permet pas la lecture ou la programmation parallèle des synapses et est limité par la bande passante reliant la mémoire à l’unité de calcul. Les technologies mémoire de type memristive pourrait permettre l’implémentation de ce parallélisme au coeur de la mémoire.Dans cette thèse, nous envisageons le développement d’un réseau de neurones impulsionnels dédié au monde de l’embarqué à base de dispositif mémoire émergents. Dans un premier temps, nous avons analysé un réseau impulsionnel afin d’optimiser ses différentes composantes : neurone, synapse et méthode d’apprentissage STDP en vue d’une implémentation numérique. Dans un second temps, nous envisageons l’implémentation de la mémoire synaptique par des dispositifs memristifs. Enfin, nous présentons le développement d’une puce co-intégrant des neurones implémentés en CMOS avec des synapses en technologie CBRAM

A new approach to unravel metabolic regulations. Application to microalgae growth and lipid production under day/night cycles and nitrogen starvation

A new approach to unravel metabolic regulations. Application to microalgae growth and lipid production under day/night cycles and nitrogen starvation. BioSynSys 2015 : 1er colloque du GDR "Biologie de Synthèse et des Systèmes

Study, optimization and silicon implementation of a smart high-voltage conditioning circuit for electrostatic vibration energy harvesting system

La récupération de l'énergie des vibrations est un concept relativement nouveau qui peut être utilisé dans l'alimentation des dispositifs embarqués de puissance à micro-échelle avec l'énergie des vibrations omniprésentes dans l environnement. Cette thèse contribue à une étude générale des récupérateurs de l'énergie des vibrations (REV) employant des transducteurs électrostatiques. Un REV électrostatique typique se compose d'un transducteur capacitif, de l'électronique de conditionnement et d un élément de stockage. Ce travail se concentre sur l'examen du circuit de conditionnement auto-synchrone proposé en 2006 par le MIT, qui combine la pompe de charge à base de diodes et le convertisseur DC-DC inductif de type de flyback qui est entraîné par le commutateur. Cette architecture est très prometteuse car elle élimine la commande de grille précise des transistors utilisés dans les architectures synchrones, tandis qu'un commutateur unique se met en marche rarement. Cette thèse propose une analyse théorique du circuit de conditionnement. Nous avons développé un algorithme qui par commutation appropriée de flyback implémente la stratégie de conversion d'énergie optimale en tenant compte des pertes liées à la commutation. En ajoutant une fonction de calibration, le système devient adaptatif pour les fluctuations de l'environnement. Cette étude a été validée par la modélisation comportementale.Une autre contribution consiste en la réalisation de l'algorithme proposé au niveau du circuit CMOS. Les difficultés majeures de conception étaient liées à l'exigence de haute tension et à la priorité de la conception faible puissance. Nous avons conçu un contrôleur du commutateur haute tension de faible puissance en utilisant la technologie AMS035HV. Sa consommation varie entre quelques centaines de nanowatts et quelques microwatts, en fonction de nombreux facteurs - paramètres de vibrations externes, niveaux de tension de la pompe de charge, la fréquence de la commutation de commutateur, la fréquence de la fonction de calibration, etc.Nous avons également réalisé en silicium, fabriqué et testé un commutateur à haute tension avec une nouvelle architecture de l'élévateur de tension de faible puissance. En montant sur des composants discrets de la pompe de charge et du circuit de retour et en utilisant l'interrupteur conçu, nous avons caractérisé le fonctionnement large bande haute-tension du prototype de transducteur MEMS fabriqué à côté de cette thèse à l'ESIEE Paris. Lorsque le capteur est excité par des vibrations stochastiques ayant un niveau d'accélération de 0,8 g rms distribué dans la bande 110-170 Hz, jusqu'à 0,75 W de la puissance nette a été récupérée.Vibration energy harvesting is a relatively new concept that can be used in powering micro-scale power embedded devices with the energy of vibrations omnipresent in the surrounding. This thesis contributes to a general study of vibration energy harvesters (VEHs) employing electrostatic transducers. A typical electrostatic VEH consists of a capacitive transducer, conditioning electronics and a storage element. This work is focused on investigations of the reported by MIT in 2006 auto-synchronous conditioning circuit, which combines the diode-based charge pump and the inductive flyback energy return driven by the switch. This architecture is very promising since it eliminates precise gate control of transistors employed in synchronous architectures, while a unique switch turns on rarely. This thesis addresses the theoretical analysis of the conditioning circuit. We developed an algorithm that by proper switching of the flyback allows the optimal energy conversion strategy taking into account the losses associated with the switching. By adding the calibration function, the system became adaptive to the fluctuations in the environment. This study was validated by the behavioral modeling. Another contribution consists in realization of the proposed algorithm on the circuit level. The major design difficulties were related to the high-voltage requirement and the low-power design priority. We designed a high-voltage analog controller of the switch using AMS035HV technology. Its power consumption varies between several hundred nanowatts and a few microwatts, depending on numerous factors - parameters of external vibrations, voltage levels of the charge pump, frequency of the flyback switching, frequency of calibration function, etc. We also implemented on silicon, fabricated and tested a high-voltage switch with a novel low power level-shifting driver. By mounting on discrete components the charge pump and flyback circuit and employing the proposed switch, we characterized the wideband high-voltage operation of the MEMS transducer prototype fabricated alongside this thesis in ESIEE Paris. When excited with stochastic vibrations having an acceleration level of 0.8 g rms distributed in the band 110-170 Hz, up to 0.75 $\mu$W of net electrical power has been harvested.PARIS-JUSSIEU-Bib.électronique (751059901) / SudocSudocFranceF

Embedded System Design

A unique feature of this open access textbook is to provide a comprehensive introduction to the fundamental knowledge in embedded systems, with applications in cyber-physical systems and the Internet of things. It starts with an introduction to the field and a survey of specification models and languages for embedded and cyber-physical systems. It provides a brief overview of hardware devices used for such systems and presents the essentials of system software for embedded systems, including real-time operating systems. The author also discusses evaluation and validation techniques for embedded systems and provides an overview of techniques for mapping applications to execution platforms, including multi-core platforms. Embedded systems have to operate under tight constraints and, hence, the book also contains a selected set of optimization techniques, including software optimization techniques. The book closes with a brief survey on testing. This fourth edition has been updated and revised to reflect new trends and technologies, such as the importance of cyber-physical systems (CPS) and the Internet of things (IoT), the evolution of single-core processors to multi-core processors, and the increased importance of energy efficiency and thermal issues