A low-complexity linear and iterative receiver architecture for multi-antenna communication systems

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Vita.Includes bibliographical references (leaves 60-62).Multi-antenna systems have been shown to significantly improve channel capacity in wireless environments. The focus of this thesis is on the design of low-complexity multi-antenna receiver architectures for communication networks and their demonstration in a real-time wireless environment. Our practical realization of an orthogonal frequency-division multi-antenna receiver is capable of several forms of linear and iterative detection. Our implementation is based on a division-free reformulation of standard minimum mean-squared-error detection algorithms and uses complex dot-products as the basic building blocks of a folded-pipelined architecture. This folded-pipelined architecture provides significant area savings over non-folded approaches. The demonstration of our receiver architecture is carried out on a rapid-prototyping FPGA communication system. This prototype is used to validate our design and complement theoretical and simulated results with real-time laboratory measurements in a typical office environment.by David Louis Milliner.M.Eng

SdrLift: A Domain-Specific Intermediate Hardware Synthesis Framework for Prototyping Software-Defined Radios

Modern design of Software-Defined Radio (SDR) applications is based on Field Programmable Gate Arrays (FPGA) due to their ability to be configured into solution architectures that are well suited to domain-specific problems while achieving the best trade-off between performance, power, area, and flexibility. FPGAs are well known for rich computational resources, which traditionally include logic, register, and routing resources. The increased technological advances have seen FPGAs incorporating more complex components that comprise sophisticated memory blocks, Digital Signal Processing (DSP) blocks, and high-speed interfacing to Gigabit Ethernet (GbE) and Peripheral Component Interconnect Express (PCIe) bus. Gateware for programming FPGAs is described at a lowlevel of design abstraction using Register Transfer Language (RTL), typically using either VHSIC-HDL (VHDL) or Verilog code. In practice, the low-level description languages have a very steep learning curve, provide low productivity for hardware designers and lack readily available open-source library support for fundamental designs, and consequently limit the design to only hardware experts. These limitations have led to the adoption of High-Level Synthesis (HLS) tools that raise design abstraction using syntax, semantics, and software development notations that are well-known to most software developers. However, while HLS has made programming of FPGAs more accessible and can increase the productivity of design, they are still not widely adopted in the design community due to the low-level skills that are still required to produce efficient designs. Additionally, the resultant RTL code from HLS tools is often difficult to decipher, modify and optimize due to the functionality and micro-architecture that are coupled together in a single High-Level Language (HLL). In order to alleviate these problems, Domain-Specific Languages (DSL) have been introduced to capture algorithms at a high level of abstraction with more expressive power and providing domain-specific optimizations that factor in new transformations and the trade-off between resource utilization and system performance. The problem of existing DSLs is that they are designed around imperative languages with an instruction sequence that does not match the hardware structure and intrinsics, leading to hardware designs with system properties that are unconformable to the high-level specifications and constraints. The aim of this thesis is, therefore, to design and implement an intermediatelevel framework namely SdrLift for use in high-level rapid prototyping of SDR applications that are based on an FPGA. The SdrLift input is a HLL developed using functional language constructs and design patterns that specify the structural behavior of the application design. The functionality of the SdrLift language is two-fold, first, it can be used directly by a designer to develop the SDR applications, secondly, it can be used as the Intermediate Representation (IR) step that is generated by a higher-level language or a DSL. The SdrLift compiler uses the dataflow graph as an IR to structurally represent the accelerator micro-architecture in which the components correspond to the fine-level and coarse-level Hardware blocks (HW Block) which are either auto-synthesized or integrated from existing reusable Intellectual Property (IP) core libraries. Another IR is in the form of a dataflow model and it is used for composition and global interconnection of the HW Blocks while making efficient interfacing decisions in an attempt to satisfy speed and resource usage objectives. Moreover, the dataflow model provides rules and properties that will be used to provide a theoretical framework that formally analyzes the characteristics of SDR applications (i.e. the throughput, sample rate, latency, and buffer size among other factors). Using both the directed graph flow (DFG) and the dataflow model in the SdrLift compiler provides two benefits: an abstraction of the microarchitecture from the high-level algorithm specifications and also decoupling of the microarchitecture from the low-level RTL implementation. Following the IR creation and model analyses is the VHDL code generation which employs the low-level optimizations that ensure optimal hardware design results. The code generation process per forms analysis to ensure the resultant hardware system conforms to the high-level design specifications and constraints. SdrLift is evaluated by developing representative SDR case studies, in which the VHDL code for eight different SDR applications is generated. The experimental results show that SdrLift achieves the desired performance and flexibility, while also conserving the hardware resources utilized

Design and validation of a scalable Digital Wireless Channel Emulator using an FPGA computing cluster

A Digital Wireless Channel Emulator (DWCE) is a system that is capable of emulating the RF environment for a group of wireless devices. The use of digital wireless channel emulators with networking radios is hampered by the inability to efficiently scale a DWCE to a large number of nodes. If such a large scale digital wireless channel emulator were to exist, a significant amount of time and money could be saved by testing networking radios in a laboratory before running lengthy and costly field tests. By utilizing the repeatability of a laboratory environment it will be possible to investigate and solve issues more quickly and efficiently. This will enable the performance of the radios to be known with a high degree of certainty before they are brought to the field. This dissertation investigates the use of an FPGA cluster configured as a distributed system to provide the computational and network structure to scale a DWCE to support 1250 or more wireless devices. This number of wireless devices is approximately two orders of magnitude larger than any other documented system. In this dissertation, the term ”scale” used for a DWCE is defined as an increase of three key factors: number of wireless devices, signal bandwidth emulated, and the fidelity of the emulation. It is possible to make tradeoffs and reduce any one of these to increase the other two. This dissertation shows a DWCE that can increase all of these factors in an efficient manner and thoroughly investigates the fidelity of the emulation it produces

Design, construction and commissioning of the Thermal Screen Control System for the CMS Tracker detector at CERN

The CERN (European Organization for Nuclear Research) laboratory is currently building the Large Hadron Collider (LHC). Four international collaborations have designed (and are now constructing) detectors able to exploit the physics potential of this collider. Among them is the Compact Muon Solenoid (CMS), a general purpose detector optimized for the search of Higgs boson and for physics beyond the Standard Model of fundamental interactions between elementary particles. This thesis presents, in particular, the design, construction, commissioning and test of the control system for a screen that provides a thermal separation between the Tracker and ECAL (Electromagnetic CALorimeter) detector of CMS (Compact Muon Solenoid experiment). Chapter 1 introduces the new challenges posed by these installations and deals, more in detail, with the Tracker detector of CMS. The size of current experiments for high energy physics is comparable to that of a small industrial plant: therefore, the techniques used for controls and regulations, although highly customized, must adopt Commercial Off The Shelf (COTS) hardare and software. The âﾜslow controlâ systems for the experiments at CERN make extensive use of PLCs (Programmable Logic Controllers) and SCADA (Supervisory Control and Data Acquisition) to provide safety levels (namely interlocks), regulations, remote control of high and low voltages distributions, as well as archiving and trending facilities. The system described in this thesis must follow the same philosophy and, at the same time, comply with international engineering standards. While the interlocks applications belong straightforwardly to the category of DES (Discrete Event System), and are therefore treated with a Finite State Machine approach, other controls are more strictly related to the regulation problem. Chapter 2 will focus on various aspects of modern process control and on the tools used to design the control system for the thermal screen: the principles upon which the controller is designed and tuned, and the model validated, including the Multiple Input-Multiple Output (MIMO) problematics are explained. The thermal screen itself, the constraints and the basis of its functioning are described in Chapter 3, where the thermodynamical design is discussed as well. For the LHC experiments, the aim of a control system is also to provide a well defined SIL (Safety Interlock Level) to keep the system in a safe condition; yet, in this case, it is necessary to regulate the temperature of the system within certain values and respect the constraints arising from the specific needs of the above mentioned subsystems. The most natural choice for a PLC-based controller is a PID (Proportional Integral Derivative) controller. This kind of controller is widely used in many industrial process, from batch production in the pharmaceutics or automotive field to chemical plants, distillation columns and, in general, wherever a reliable and robust control is needed. In order to design and tune PID controllers, many techniques are in use; the approach followed in this thesis is that of black-box modeling: the system is modeled in the time domain, a transfer function is inferred and a controller is designed. Then, a system identification procedure allows for a more thorough study and validation of the model, and for the controller tuning. Project of the thermal screen control including system modeling, controller design and MIMO implementation issues are entirely covered in Chapter 4. A systems engineering methodology has been followed all along to adequately manage and document every phase of the project, complying with time and budget constraints. A risk analysis has been performed, using Layer of Protection Analysis (LOPA) and Hazard and Operability Studies (HAZOP), to understand the level of protection assured by the thermal screen and its control components. Tests planned and then performed to validate the model and for quality assurance purposes are described in Chapter 5. A climatic chamber has been designed and built at CERN, where the real operating conditions of the thermal screen are simulated. Detailed test procedures have been defined, following IEEE standards, in order to completely check every single thermal screen panel. This installation allows for a comparison of different controller tuning approaches, including IAE minimization, Skogestad tuning rules, Internal Model Control (IMC), and a technique based upon the MatLab Optimization toolbox. This installation is also used for system identification purposes and for the acceptance tests of every thermal screen panel (allowing for both electrical and hydraulic checks). Also, tests have been performed on the West Hall CERN experimental area , where a full control system has been set up, for interlock high- and low- voltage lines. The interlock system operating procedures and behaviour have been validated during real operating conditions of the detector esposed to a particle beam. The satisfactory results of tests take the project to full completion, allowing the plan to reach the âﾜexitâ stage, when the thermal screen is ready to be installed in the Tracker and ready to be operational

Expanding the Horizons of Manufacturing: Towards Wide Integration, Smart Systems and Tools

This research topic aims at enterprise-wide modeling and optimization (EWMO) through the development and application of integrated modeling, simulation and optimization methodologies, and computer-aided tools for reliable and sustainable improvement opportunities within the entire manufacturing network (raw materials, production plants, distribution, retailers, and customers) and its components. This integrated approach incorporates information from the local primary control and supervisory modules into the scheduling/planning formulation. That makes it possible to dynamically react to incidents that occur in the network components at the appropriate decision-making level, requiring fewer resources, emitting less waste, and allowing for better responsiveness in changing market requirements and operational variations, reducing cost, waste, energy consumption and environmental impact, and increasing the benefits. More recently, the exploitation of new technology integration, such as through semantic models in formal knowledge models, allows for the capture and utilization of domain knowledge, human knowledge, and expert knowledge toward comprehensive intelligent management. Otherwise, the development of advanced technologies and tools, such as cyber-physical systems, the Internet of Things, the Industrial Internet of Things, Artificial Intelligence, Big Data, Cloud Computing, Blockchain, etc., have captured the attention of manufacturing enterprises toward intelligent manufacturing systems

Aerial Networking: Creating a Resilient Wireless Network for Multiple Unmanned Aerial Vehicles

The goal of this report is to design the groundwork of a wireless communications system between several Unmanned Aerial Vehicles (UAVs) that will help conduct Search and Rescue (SAR) missions. UAVs could help with these missions because they can provide aerial reconnaissance at low cost and risk. To maximize efficiency, the architecture of our ad hoc network includes several UAVs with cameras (drones) relaying their data through a central UAV called a mothership. Our specific objectives, which we successfully met, were to demonstrate the feasibility of such a network in the laboratory and to lay the groundwork for the physical implementation of the system, including the assembly of a motherboard and Wi-Fi transmitters that will perform the communication between the user and UAVs

Micro/Nano Structures and Systems

Micro/Nano Structures and Systems: Analysis, Design, Manufacturing, and Reliability is a comprehensive guide that explores the various aspects of micro- and nanostructures and systems. From analysis and design to manufacturing and reliability, this reprint provides a thorough understanding of the latest methods and techniques used in the field. With an emphasis on modern computational and analytical methods and their integration with experimental techniques, this reprint is an invaluable resource for researchers and engineers working in the field of micro- and nanosystems, including micromachines, additive manufacturing at the microscale, micro/nano-electromechanical systems, and more. Written by leading experts in the field, this reprint offers a complete understanding of the physical and mechanical behavior of micro- and nanostructures, making it an essential reference for professionals in this field

Developing and Testing an Anguilliform Robot Swimming with Theoretically High Hydrodynamic Efficiency

An anguilliform swimming robot replicating an idealized motion is a complex marine vehicle necessitating both a theoretical and experimental analysis to completely understand its propulsion characteristics. The ideal anguilliform motion within is theorized to produce ``wakeless\u27\u27 swimming (Vorus, 2011), a reactive swimming technique that produces thrust by accelerations of the added mass in the vicinity of the body. The net circulation for the unsteady motion is theorized to be eliminated. The robot was designed to replicate the desired, theoretical motion by applying control theory methods. Independent joint control was used due to hardware limitations. The fluid velocity vectors in the propulsive wake downstream of the tethered, swimming robot were measured using Particle Image Velocimetry (PIV). Simultaneously, a load cell measured the thrust (or drag) forces of the robot via a hydrodynamic tether. The measured field velocities and thrust forces were compared to the theoretical predictions for each. The desired, ideal motion was not replicated consistently during PIV testing, producing off-design scenarios. The thrust-computing method for the ideal motion was applied to the actual, recorded motion and compared to the load cell results. The theoretical field velocities were computed differently by accounting for shed vortices due to a different shape than ideal. The theoretical thrust shows trends similar to the measured thrust over time. Similarly promising comparisons are found between the theoretical and measured flow-field velocities with respect to qualitative trends and velocity magnitudes. The initial thrust coefficient prediction was deemed insufficient, and a new one was determined from an iterative process. The off-design cases shed flow structures into the downstream wake of the robot. The first is a residual disturbance of the shed boundary layer, which is to be expected for the ideal case, and dissipates within one motion cycle. The second are larger-order vortices that are being shed at two distinct times during a half-cycle. These qualitative and quantitative comparisons were used to confirm the possibility of the original hypothesis of ``wakeless\u27\u27 swimming. While the ideal motion could not be tested consistently, the results of the off-design cases agree significantly with the adjusted theoretical computations. This shows that the boundary conditions derived from slender-body constraints and the assumptions of ideal flow theory are sufficient enough to predict the propulsion characteristics of an anguilliform robot undergoing this specific motion