From MARTE to Reconfigurable NoCs: A model driven design methodology

Due to the continuous exponential rise in SoC's design complexity, there is a critical need to find new seamless methodologies and tools to handle the SoC co-design aspects. We address this issue and propose a novel SoC co-design methodology based on Model Driven Engineering and the MARTE (Modeling and Analysis of Real-Time and Embedded Systems) standard proposed by Object Management Group, to raise the design abstraction levels. Extensions of this standard have enabled us to move from high level specifications to execution platforms such as reconfigurable FPGAs. In this paper, we present a high level modeling approach that targets modern Network on Chips systems. The overall objective: to perform system modeling at a high abstraction level expressed in Unified Modeling Language (UML); and afterwards, transform these high level models into detailed enriched lower level models in order to automatically generate the necessary code for final FPGA synthesis

On Energy Efficient Computing Platforms

In accordance with the Moore's law, the increasing number of on-chip integrated transistors has enabled modern computing platforms with not only higher processing power but also more affordable prices. As a result, these platforms, including portable devices, work stations and data centres, are becoming an inevitable part of the human society. However, with the demand for portability and raising cost of power, energy efficiency has emerged to be a major concern for modern computing platforms. As the complexity of on-chip systems increases, Network-on-Chip (NoC) has been proved as an efficient communication architecture which can further improve system performances and scalability while reducing the design cost. Therefore, in this thesis, we study and propose energy optimization approaches based on NoC architecture, with special focuses on the following aspects. As the architectural trend of future computing platforms, 3D systems have many bene ts including higher integration density, smaller footprint, heterogeneous integration, etc. Moreover, 3D technology can signi cantly improve the network communication and effectively avoid long wirings, and therefore, provide higher system performance and energy efficiency. With the dynamic nature of on-chip communication in large scale NoC based systems, run-time system optimization is of crucial importance in order to achieve higher system reliability and essentially energy efficiency. In this thesis, we propose an agent based system design approach where agents are on-chip components which monitor and control system parameters such as supply voltage, operating frequency, etc. With this approach, we have analysed the implementation alternatives for dynamic voltage and frequency scaling and power gating techniques at different granularity, which reduce both dynamic and leakage energy consumption. Topologies, being one of the key factors for NoCs, are also explored for energy saving purpose. A Honeycomb NoC architecture is proposed in this thesis with turn-model based deadlock-free routing algorithms. Our analysis and simulation based evaluation show that Honeycomb NoCs outperform their Mesh based counterparts in terms of network cost, system performance as well as energy efficiency.Siirretty Doriast

Advances in Computer Science and Engineering

The book Advances in Computer Science and Engineering constitutes the revised selection of 23 chapters written by scientists and researchers from all over the world. The chapters cover topics in the scientific fields of Applied Computing Techniques, Innovations in Mechanical Engineering, Electrical Engineering and Applications and Advances in Applied Modeling

Computational Augmentation of Model Based System Engineering: Supporting Mechatronic System Model Development with AI Technologies

Efforts in applying computational support for automatic design synthesis and configuration generation as well as efforts to support descriptive and computational model development for system design and verification has been approached with semantic formalisation of modelling languages and of generic structural and functional concepts using meta-models. Modelling the system using descriptive models helps the designer to explicitly document dependencies between properties and parameters of system and external entities. The descriptive models thus produced often do not consider physics based justification for presence and/or absence of relations. It is often the case, the simulation results obtained at later stages requires changing requirements as well as modifying logical (modelling relations between high level functions parameters/properties and parameters/properties of high level entities) and physical architectures (modelling relations between component’s parameters and properties) to accommodate those requirements. The current MBSE (Model Based System Engineering) tools have capabilities to verify construction of models according to predefined model formats i.e. meta-models. However, these tools and current research in augmenting capabilities of these tools lacks the focus on evaluating content inside the models i.e. whether the system modelled by models represents a system that can be physically realized. This work has tried to avail the potential of available AI (Artificial Intelligence) technologies for assisting modelling activities performed for requirement definition and analysis, architecture design and verification phase of system development process by directing designer to tools that can formalise outputs of model development activities. The proposed problem formulation is based on the insight that a system modelled at both conceptual and detailed design level can be represented by logical and mathematical relations between the properties and parameters of internal and external components or functions of the system and domain. Therefore formulation defines concepts used in requirement, logical architecture and physical architecture models using relation between parameters and properties in those models. Concepts, such as operational requirements (or non-functional requirements for particular use case scenario), are defined through the usage of sets and linking value domains of those sets to particular system application domain for which system model is being developed. These relations enables systematic elaboration of requirements into logical and physical architecture models as well as storage and retrieval of existing model knowledge using existing AI tools. A novel framework has been developed to retrieve existing descriptive structure and function models using logical reasoning as well as to retrieve existing simulation models stored in embedding space of auto-encoder neural network. Beside adopting the concepts of semantic formalisation and meta-model based descriptive knowledge retrieval it utilises novel application of unsupervised representation learning capability of neural network auto-encoders to store known physically and technologically feasible designs in low dimensional representation that cluster similar designs therefore inducing similarity or distance metric that can be used to retrieve the known design with similar behaviour as new required behaviour. Framework also enable application of generic and domain specific logical constraints (as other works has done before) and introduces new concept of system application domain to ensures that at every stage of the model development leading to conceptual physical design architecture stays inside the physical constraints as per system usage domain. The instantiated meta-model elements which are classified to a system application domain (SAD) are implicitly constraint by system usage context constraints (e.g. parameter value restriction), similarly known simulation models can also be categorised to different SADs. The proposed framework extends the conventional approach of automated design synthesis which is only based only on decomposition of high level function (summarizing input to output mapping) into basic functions and selecting components to realize those basic functions. "A system is designed with the aim that it can execute its function(s) as per performance requirements of that function(s) in required operational conditions"- By concentrating on this statement it can be seen that conventional approach of functional decomposition and function allocation to known structural components cannot guarantee to yield a working system in required scenarios by ignoring the dependencies between environment or operating conditions and operating modes of prospective designs satisfying high level function. The results obtained from the implementation of domain specific knowledge representation and retrieval (involving mixture of numerical and logical constraints) as well as the results obtained from implementation of neural network auto-encoder for representation and retrieval of domain specific simulation model demonstrates the viability of these technologies to support the proposed framework

Γ (Gamma): cloud-based analog circuit design system

Includes bibliographical references.2016 Summer.With ever increasing demand for lower power consumption, lower cost, and higher performance, designing analog circuits to meet design specifications has become an increasing challenging task, On one hand, analog circuit designers must have intimate knowledge about the underlining silicon process technology's capability to achieve the desired specifications. On the other hand, they must understand the impact of tweaking circuits to satisfy a given specification on all circuit performance parameters. Analog designers have traditionally learned to tackle design problems with numerous circuit simulations using accurate circuit simulators such as SPICE, and have increasingly relied on trial-and-error approaches to reach a converging point. However, the increased complexity with each generation of silicon technology and high dimensionality of searching for solutions, even for some simple analog circuits, have made trial-and-error approaches extremely inefficient, causing long design cycles and often missed market opportunities. Novel rapid and accurate circuit evaluation methods that are tightly integrated with circuit search and optimization methods are needed to aid design productivity. Furthermore, the current design environment with fully distributed licensing and supporting structures is cumbersome at best to allow efficient and up-to-date support for design engineers. With increasing support and licensing costs, fewer and fewer design centers can afford it. Cloud-based software as a service (SaaS) model provides new opportunities for CAD applications. It enables immediate software delivery and update to customers at very low cost. SaaS tools benefit from fast feedback and sharing channels between users and developers and run on hardware resources tailored and provided for them by software vendors. However, web-based tools must perform in a very short turn-around schedule and be always responsive. A new class of analog design tools is presented in this dissertation. The tools provide effective design aid to analog circuit designers with a dash-board control of many important circuit parameters. Fast and accurate circuit evaluations are achieved using a novel lookup-table transistor models (LUT) with novel built-in features tightly integrated with the search engine to achieve desired speed and accuracy. This enables circuit evaluation time several orders faster than SPICE simulations. The proposed architecture for analog design attempts to break the traditional analog design flow using SPICE based trial-and-error methods by providing designers with useful information about the effects of prior design decisions they have made and potential next steps they can take to meet specifications. Benefiting from the advantages offered by web-hosted architectures, the proposed architecture incorporates SaaS as its operating model. The application of the proposed architecture is illustrated by an analog circuit sizer and optimizer. The Γ (Gamma) sizer and optimizer show how web-based design-decision supporting tool can help analog circuit designers to reduce design time and achieve high quality circuit

Generating Programming Environments with Integrated Text and Graphics for VLSI Design Systems

The constant improvements in device integration, the development of new technologies and the emergence of new design techniques call for flexible, maintainable and robust software tools. The generic nature of compiler-compiler systems, with their semi-formal specifications, can help in the construction of those tools. This thesis describes the Wright editor generator which is used in the synthesis of language-based graphical editors (LBGEs). An LBGE is a programming environment where the programs being manipulated denote pictures. Editing actions can be specified through both textual and graphical interfaces. Editors generated by the Wright system are specified using the formalism of attribute grammars. The major example editor in this thesis, Stick-Wright, is a design entry system for the construction of VLSI circuits. Stick-Wright is a hierarchical symbolic layout editor which exploits a combination of text and graphics in an interactive environment to provide the circuit designer with a tool for experimenting with circuit topologies. A simpler system, Pict-Wright: a picture drawing system, is also used to illustrate the attribute grammar specification process. This thesis aims to demonstrate the efficacy of formal specification in the generation of software-tools. The generated system Stick-Wright shows that a text/graphic programming environment can form the basis of a powerful VLSI design tool, especially with regard to providing the designer with immediate graphical feedback. Further applications of the LBGE generator approach to system design are given for a range of VLSI design activities

Logic, parallelism and semantic networks : the binary predicate execution model

This thesis develops the Binary Predicate Execution Model; a distributed, massively-parallel system for semantic networks and knowledge bases that is built on a subset of first-order predicate logic. The use of logic gives the model an easily-understood programming paradigm and a well-defined semantics of execution. When expressed in binary predicates, a simple graphical interpretation can be used. All program facts are represented in an assertion graph. Each vertex is associated with a term appearing in a fact and the edges are labeled with the predicate names. Similar graphs are also associated with each rule body and the query. Finding all possible solutions corresponds to finding all possible matches between the query graph and the assertion graph. Invoking a rule corresponds to substituting the graph of its body constrained by the dependencies between its arguments. This can be implemented in a parallel, message-passing fashion where the assertion graph vertices are active processing elements which asynchronously exchange messages identifying different parts of the query that remain to be matched and containing any binding information from previous matching required to accomplish this. The model is data-driven since every message can be immediately processed without the need for any centralized control or centralized memory. By restricting how functional terms can occur, distributed data structures and remote data look-ups for unification are eliminated. Thus, the model's performance on increasingly larger problems scales-up given increasingly larger machines in most cases. Architectural support for the model is investigated and simulation results of a relatively simple software implementation are reported. This suggests performance on the order of 10^5 logical inferences per second for 256 processing elements in an n-cube configuration. Further research directions, including that of increasing efficiency, are discussed