Network emulation focusing on QoS-Oriented satellite communication

This chapter proposes network emulation basics and a complete case study of QoS-oriented Satellite Communication

A Taxonomy for Congestion Control Algorithms in Vehicular Ad Hoc Networks

One of the main criteria in Vehicular Ad hoc Networks (VANETs) that has attracted the researchers' consideration is congestion control. Accordingly, many algorithms have been proposed to alleviate the congestion problem, although it is hard to find an appropriate algorithm for applications and safety messages among them. Safety messages encompass beacons and event-driven messages. Delay and reliability are essential requirements for event-driven messages. In crowded networks where beacon messages are broadcasted at a high number of frequencies by many vehicles, the Control Channel (CCH), which used for beacons sending, will be easily congested. On the other hand, to guarantee the reliability and timely delivery of event-driven messages, having a congestion free control channel is a necessity. Thus, consideration of this study is given to find a solution for the congestion problem in VANETs by taking a comprehensive look at the existent congestion control algorithms. In addition, the taxonomy for congestion control algorithms in VANETs is presented based on three classes, namely, proactive, reactive and hybrid. Finally, we have found the criteria in which fulfill prerequisite of a good congestion control algorithm

A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)

Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multi-core neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.Comment: 17 pages, 14 figure

Towards an unified experimentation framework for protocol engineering

The design and development process of complex systems require an adequate methodology and efficient instrumental support in order to early detect and correct anomalies in the functional and non-functional properties of the solution. In this article, an Unified Experimentation Framework (UEF) providing experimentation facilities at both design and development stages is introduced. This UEF provides a mean to achieve experiment in both simulation mode with UML2 models of the designed protocol and emulation mode using real protocol implementation. A practical use case of the experimentation framework is illustrated in the context of satellite environment