Ultra-thin plasma nitrided oxide gate dielectrics for advanced MOS transistors

Ultra-thin plasma nitrided oxides have been optimized with the objective to decrease JG and maximize carrier mobility. It was found that while the base oxide cannot be aggressively scaled, plasma optimization yields better mobility thereby increase transistor performance. A summary of the EOT versus gate leakage current density of NMOS devices with plasma nitrided oxides is shown in Figure 5.19. EOT down to 1.2 nm has been achieved with a gate leakage current density of 40 A/cm2 at 1 V operating voltage

Three-Dimensional MOS Process Development

A novel MOS technology for three-dimensional integration of electronic circuits on silicon substrates was developed. Selective epitaxial growth and epitaxial lateral overgrowth of monocrystalline silicon over oxidized silicon were employed to create locally restricted silicon-on-insulator device islands. Thin gate oxides were discovered to deteriorate in ambients typically used for selective epitaxial growth. Conditions of general applicability to silicon epitaxy systems were determined under which this deterioration was greatly reduced. Selective epitaxial growth needed to be carried out at low temperatures. However, crystalline defects increase as deposition temperatures are decreased. An exact dependence between the residual moisture content in epitaxial growth ambients, deposition pressure, and deposition temperature was determined which is also generally applicable to silicon epitaxy systems. The dependences of growth rates and growth rate uniformity on loading, temperature, flow rates, gas composition, and masking oxide thickness were investigated for a pancake type epitaxy reactor. A conceptual model was discussed attempting to describe the effects peculiar to selective epitaxial growth. The newly developed processing steps were assembled to fabricate three dimensional silicon-on-insulator capacitors. These capacitors were electrically evaluated. Surface state densities were in the order of 1O11cm-2 eV-1 and therefore within the range of applicability for a practical CMOS process. Oxidized polysilicon gates were overgrown with silicon by epitaxial lateral overgrowth. The epitaxial silicon was planarized and source and drain regions were formed above the polysilicon gates in Silicon-on-insulator material. The modulation of the source-drain current by bias changes of the buried gate was demonstrated

Development and characterization of high performance transistors on glass

Currently, the electrical drivers behind active-matrix flat-panel displays are polysilicon or amorphous silicon based thin-film transistors (TFTs). The ability to integrate transistors onto the glass substrate offers certain design and performance advantages over package-level integration with bulk silicon ICs; this is commonly referred to as system-on-glass (SOG) or system-on-panel (SOP). System on glass may also lower the manufacturing costs of the entire product. Cell phones, personal digital assistants, and entertainment systems are examples of applications that would benefit from system on glass integration. This project is a joint effort between the Microelectronic Engineering Department at RIT and Corning Incorporated. Thin- film transistors have been fabricated on a new substrate material which consists of a high-quality silicon layer on Corning’s Eagle 2000 flat-panel display glass. The substrate material has the potential of yielding transistors with higher performance than commercialized polysilicon and amorphous silicon thin film transistor technologies. The primary focus of this investigation was to solve the engineering challenges of dopant activation, deposited dielectric quality and interface charge associated with a low-temperature (LT) process. A process that is compatible with the thermal constraints of the glass has been designed and demonstrated through the fabrication of MOS transistor. While the device characteristics demonstrate the on-state and off-state behavior of standard bulk-silicon devices, there are unique features which required an extensive study to understand and explain the governing physics. Device simulation was used to develop a comprehensive model of operation for the devices

Development of a fully-depleted thin-body FinFET process

The goal of this work is to develop the processes needed for the demonstration of a fully-depleted (FD) thin-body fin field effect transistor (FinFET). Recognized by the 2003 International Technology Roadmap for Semiconductors as an emerging non-classical CMOS technology, FinFETs exhibit high drive current, reduced short-channel effects, an extreme scalability to deep submicron regimes. The approach used in this study will build on previous FinFET research, along with new concepts and technologies. The critical aspects of this research are: (1) thin body creation using spacer etchmasks and oxidation/etchback schemes, (2) use of an oxynitride gate dielectric, (3) silicon crystal orientation effect evaluation, and (4) creation of fully-depleted FinFET devices of submicron gate length on Silicon-on-Insulator (SOI) substrates. The developed process yielded functional FinFETs of both thin body and wide body variety. Electrical tests were employed to describe device behaviour, including their subthreshold characteristics, standard operation, effects of gate misalignment on device performance, and impact of crystal orientation on device drive current. The process is shown to have potential for deep submicron regimes of fin width and gate length, and provides a good foundation for further research of FinFETs and similar technologies at RIT

Local Epitaxial Overgrowth for Stacked Complementary MOS Transistor Pairs

A three-dimensional silicon processing technology for CMOS circuits was developed and characterized. The first fully depleted SOI devices with individually biasable gates on both sides of the silicon film were realized. A vertically stacked CMOS Inverter built by lateral overgrowth was reported for the first time. Nucleation-free epitaxial lateral overgrowth of silicon over thin oxides was developed for both a pancake and a barrel-type epitaxy reactor: This process was optimized to limit damage to gate oxides and minimize dopant diffusion within the Substrate. Autodoping from impurities of the MOS transistors built in the substrate was greatly reduced. A planarisation technique was developed to reduce the silicon film thickness from 13μm to below 0.5μm for full depletion. Chemo-mechanical polishing was modified to yield an automatic etch stop with the corresponding control and uniformity of the silicon film. The resulting wafer topography is more planar than in a conventional substrate CMOS process. PMOS transistors which match the current drive of bulk NM0S devices of equal geometry were characterized, despite the three-times lower hole mobility. Devices realized in the substrate, at the bottom and on top of the SOI film were essentially indistinguishable from bulk devices. A novel device with two insulated gates controlling the same channel was characterized. Inverters were realized both as joint-gate configuration and with symmetric performance of n- and p-channel. These circuits were realized in the area of a single NMOS transistor

Polysilicon Emitter Fabrication and Modeling

The research proposed for 1986 was to develop the technology for fabricating, measuring, and computer modeling the polysilicon emitter bipolar transistor. Fabrication consisted of producing three types of bipolar transistors; a regular bipolar device to act as the control, a polysilicon contacted emitter transistor, and a polysilicon emitter directly on the base region with a very thin oxide at the interface. The proposed fabrication research concentrated on investigating a new method of fabricating polysilicon contacted emitter bipolar transistors. The new fabrication technique uses plasma etching of the emitter location on the base region and, without breaking vacuum, depositing amorphous silicon (a-Si) on the cleaned interface. The a-Si was then to be doped by ion-implantation and heated to 600-700 C ° to produce the polysilicon emitter contact. The controlled interface and the fine grained polysilicon should lead to more uniform and predictable betas for the polycontacted transistors. Both polysilicon contacted emitters and polysilicon emitters were to be investigated over a range of base doping. We proposed the modeling work in two directions: l) 2-D simulation so that small geometry transistors can be accurately modeled and 2) simulation of polysilicon contacted emitter transistors. Measurements on the devices described above will be used to develop a polysilicon model. The objective of this part of the project is to develop a numerical device simulator with predictive capability, i.e. one that can be used with confidence in place of actual device fabrication. The numerical device models will be provided to Delco and should find many applications in development and manufacturing. The fabrication highlights of the 1986 work were the design and fabrication of preliminary bipolar transistors and polysilicon emitters, the design and layout of the test wafer, and the fabrication and measurements on shallow arsenic doped emitter devices. There were 22 sets of fabrication runs made beyond the preliminary devices. The last results of these runs show that the shallow Arsenic emitter (0.05 /i) and the very narrow base width (0.1 y) control devices with metal emitter contact, have an average peak beta of about 75. Poly contacted emitter devices fabricated at the same time on the same wafer show a beta enhancement to 232, a factor of about 2.7 to 3.0 in the average peak beta. The polysilicon was deposited in a standard way in a LPCVD tube. We are presently fabricating polysilicon devices for studying the effects of the methods used in treating the surfaces before the poly is deposited and the way the poly is formed (amorphous PELPCYD)