4,950 research outputs found
The IPS fidelity scale as a guideline to implement Supported Employment
info:eu-repo/semantics/publishe
Science and Applications Space Platform (SASP) End-to-End Data System Study
The capability of present technology and the Tracking and Data Relay Satellite System (TDRSS) to accommodate Science and Applications Space Platforms (SASP) payload user's requirements, maximum service to the user through optimization of the SASP Onboard Command and Data Management System, and the ability and availability of new technology to accommodate the evolution of SASP payloads were assessed. Key technology items identified to accommodate payloads on a SASP were onboard storage devices, multiplexers, and onboard data processors. The primary driver is the limited access to TDRSS for single access channels due to sharing with all the low Earth orbit spacecraft plus shuttle. Advantages of onboard data processing include long term storage of processed data until TRDSS is accessible, thus reducing the loss of data, eliminating large data processing tasks at the ground stations, and providing a more timely access to the data
Compiler and Architecture Design for Coarse-Grained Programmable Accelerators
abstract: The holy grail of computer hardware across all market segments has been to sustain performance improvement at the same pace as silicon technology scales. As the technology scales and the size of transistors shrinks, the power consumption and energy usage per transistor decrease. On the other hand, the transistor density increases significantly by technology scaling. Due to technology factors, the reduction in power consumption per transistor is not sufficient to offset the increase in power consumption per unit area. Therefore, to improve performance, increasing energy-efficiency must be addressed at all design levels from circuit level to application and algorithm levels.
At architectural level, one promising approach is to populate the system with hardware accelerators each optimized for a specific task. One drawback of hardware accelerators is that they are not programmable. Therefore, their utilization can be low as they perform one specific function. Using software programmable accelerators is an alternative approach to achieve high energy-efficiency and programmability. Due to intrinsic characteristics of software accelerators, they can exploit both instruction level parallelism and data level parallelism.
Coarse-Grained Reconfigurable Architecture (CGRA) is a software programmable accelerator consists of a number of word-level functional units. Motivated by promising characteristics of software programmable accelerators, the potentials of CGRAs in future computing platforms is studied and an end-to-end CGRA research framework is developed. This framework consists of three different aspects: CGRA architectural design, integration in a computing system, and CGRA compiler. First, the design and implementation of a CGRA and its instruction set is presented. This design is then modeled in a cycle accurate system simulator. The simulation platform enables us to investigate several problems associated with a CGRA when it is deployed as an accelerator in a computing system. Next, the problem of mapping a compute intensive region of a program to CGRAs is formulated. From this formulation, several efficient algorithms are developed which effectively utilize CGRA scarce resources very well to minimize the running time of input applications. Finally, these mapping algorithms are integrated in a compiler framework to construct a compiler for CGRADissertation/ThesisDoctoral Dissertation Computer Science 201
System Synthesis for Networks of Programmable Blocks
The advent of sensor networks presents untapped opportunities for synthesis.
We examine the problem of synthesis of behavioral specifications into networks
of programmable sensor blocks. The particular behavioral specification we
consider is an intuitive user-created network diagram of sensor blocks, each
block having a pre-defined combinational or sequential behavior. We synthesize
this specification to a new network that utilizes a minimum number of
programmable blocks in place of the pre-defined blocks, thus reducing network
size and hence network cost and power. We focus on the main task of this
synthesis problem, namely partitioning pre-defined blocks onto a minimum number
of programmable blocks, introducing the efficient but effective PareDown
decomposition algorithm for the task. We describe the synthesis and simulation
tools we developed. We provide results showing excellent network size
reductions through such synthesis, and significant speedups of our algorithm
over exhaustive search while obtaining near-optimal results for 15 real network
designs as well as nearly 10,000 randomly generated designs.Comment: Submitted on behalf of EDAA (http://www.edaa.com/
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