Solutions pour l'auto-adaptation des systèmes sans fil

The current demand on ubiquitous connectivity imposes stringent requirements on the fabrication of Radio-Frequency (RF) circuits. Designs are consequently transferred to the most advanced CMOS technologies that were initially introduced to improve digital performance. In addition, as technology scales down, RF circuits are more and more susceptible to a lot of variations during their lifetime, as manufacturing process variability, temperature, environmental conditions, aging… As a result, the usual worst-case circuit design is leading to sub-optimal conditions, in terms of power and/or performance most of the time for the circuit. In order to counteract these variations, increasing the performances and also reduce power consumption, adaptation strategies must be put in place.More importantly, the fabrication process introduces more and more performance variability, which can have a dramatic impact on the fabrication yield. That is why RF designs are not easily fabricated in the most advanced CMOS technologies, as 32nm or 22nm nodes for instance. In this context, the performances of RF circuits need to be calibrated after fabrication so as to take these variations into account and recover yield loss.This thesis work is presenting on a post-fabrication calibration technique for RF circuits. This technique is performed during production testing with minimum extra cost, which is critical since the cost of test can be comparable to the cost of fabrication concerning RF circuits and cannot be further raised. Calibration is enabled by equipping the circuit with tuning knobs and sensors. Optimal tuning knob identification is achieved in one-shot based on a single test step that involves measuring the sensor outputs once. For this purpose, we rely on variation-aware sensors which provide measurements that remain invariant under tuning knob changes. As an auxiliary benefit, the variation-aware sensors are non-intrusive and totally transparent to the circuit.Our proposed methodology has first been demonstrated with simulation data with an RF power amplifier as a case study. Afterwards, a silicon demonstrator has then been fabricated in a 65nm technology in order to fully demonstrate the methodology. The fabricated dataset of circuits is extracted from typical and corner wafers. This feature is very important since corner circuits are the worst design cases and therefore the most difficult to calibrate. In our case, corner circuits represent more than the two third of the overall dataset and the calibration can still be proven. In details, fabrication yield based on 3 sigma performance specifications is increased from 21% to 93%. This is a major performance of the technique, knowing that worst case circuits are very rare in industrial fabrication.La demande courante de connectivité instantanée impose un cahier des charges très strict sur la fabrication des circuits Radio-Fréquences (RF). Les circuits doivent donc être transférées vers les technologies les plus avancées, initialement introduites pour augmenter les performances des circuits purement numériques. De plus, les circuits RF sont soumis à de plus en plus de variations et cette sensibilité s’accroît avec l’avancées des technologies. Ces variations sont par exemple les variations du procédé de fabrication, la température, l’environnement, le vieillissement… Par conséquent, la méthode classique de conception de circuits “pire-cas” conduit à une utilisation non-optimale du circuit dans la vaste majorité des conditions, en termes de performances et/ou de consommation. Ces variations doivent donc être compensées, en utilisant des techniques d’adaptation.De manière plus importante encore, le procédé de fabrication des circuits introduit de plus en plus de variabilité dans les performances des circuits, ce qui a un impact important sur le rendement de fabrication des circuits. Pour cette raison, les circuits RF sont difficilement fabriqués dans les technologies CMOS les plus avancées comme les nœuds 32nm ou 22nm. Dans ce contexte, les performances des circuits RF doivent êtres calibrées après fabrication pour prendre en compte ces variations et retrouver un haut rendement de fabrication.Ce travail de these présente une méthode de calibration post-fabrication pour les circuits RF. Cette méthodologie est appliquée pendant le test de production en ajoutant un minimum de coût, ce qui est un point essentiel car le coût du test est aujourd’hui déjà comparable au coût de fabrication d’un circuit RF et ne peut être augmenté d’avantage. Par ailleurs, la puissance consommée est aussi prise en compte pour que l’impact de la calibration sur la consommation soit minimisé. La calibration est rendue possible en équipant le circuit avec des nœuds de réglages et des capteurs. L’identification de la valeur de réglage optimale du circuit est obtenue en un seul coup, en testant les performances RF une seule et unique fois. Cela est possible grâce à l’utilisation de capteurs de variations du procédé de fabrication qui sont invariants par rapport aux changements des nœuds de réglage. Un autre benefice de l’utilisation de ces capteurs de variation sont non-intrusifs et donc totalement transparents pour le circuit sous test. La technique de calibration a été démontrée sur un amplificateur de puissance RF utilisé comme cas d’étude. Une première preuve de concept est développée en utilisant des résultats de simulation.Un démonstrateur en silicium a ensuite été fabriqué en technologie 65nm pour entièrement démontrer le concept de calibration. L’ensemble des puces fabriquées a été extrait de trois types de wafer différents, avec des transistors aux performances lentes, typiques et rapides. Cette caractéristique est très importante car elle nous permet de considérer des cas de procédé de fabrication extrêmes qui sont les plus difficiles à calibrer. Dans notre cas, ces circuits représentent plus des deux tiers des puces à disposition et nous pouvons quand même prouver notre concept de calibration. Dans le détails, le rendement de fabrication passe de 21% avant calibration à plus de 93% après avoir appliqué notre méthodologie. Cela constitue une performance majeure de notre méthodologie car les circuits extrêmes sont très rares dans une fabrication industrielle

Constraint-driven RF test stimulus generation and built-in test

With the explosive growth in wireless applications, the last decade witnessed an ever-increasing test challenge for radio frequency (RF) circuits. While the design community has pushed the envelope far into the future, by expanding CMOS process to be used with high-frequency wireless devices, test methodology has not advanced at the same pace. Consequently, testing such devices has become a major bottleneck in high-volume production, further driven by the growing need for tighter quality control. RF devices undergo testing during the prototype phase and during high-volume manufacturing (HVM). The benchtop test equipment used throughout prototyping is very precise yet specialized for a subset of functionalities. HVM calls for a different kind of test paradigm that emphasizes throughput and sufficiency, during which the projected performance parameters are measured one by one for each device by automated test equipment (ATE) and compared against defined limits called specifications. The set of tests required for each product differs greatly in terms of the equipment required and the time taken to test individual devices. Together with signal integrity, precision, and repeatability concerns, the initial cost of RF ATE is prohibitively high. As more functionality and protocols are integrated into a single RF device, the required number of specifications to be tested also increases, adding to the overall cost of testing, both in terms of the initial and recurring operating costs. In addition to the cost problem, RF testing proposes another challenge when these components are integrated into package-level system solutions. In systems-on-packages (SOP), the test problems resulting from signal integrity, input/output bandwidth (IO), and limited controllability and observability have initiated a paradigm shift in high-speed analog testing, favoring alternative approaches such as built-in tests (BIT) where the test functionality is brought into the package. This scheme can make use of a low-cost external tester connected through a low-bandwidth link in order to perform demanding response evaluations, as well as make use of the analog-to-digital converters and the digital signal processors available in the package to facilitate testing. Although research on analog built-in test has demonstrated hardware solutions for single specifications, the paradigm shift calls for a rather general approach in which a single methodology can be applied across different devices, and multiple specifications can be verified through a single test hardware unit, minimizing the area overhead. Specification-based alternate test methodology provides a suitable and flexible platform for handling the challenges addressed above. In this thesis, a framework that integrates ATE and system constraints into test stimulus generation and test response extraction is presented for the efficient production testing of high-performance RF devices using specification-based alternate tests. The main components of the presented framework are as follows: Constraint-driven RF alternate test stimulus generation: An automated test stimulus generation algorithm for RF devices that are evaluated by a specification-based alternate test solution is developed. The high-level models of the test signal path define constraints in the search space of the optimized test stimulus. These models are generated in enough detail such that they inherently define limitations of the low-cost ATE and the I/O restrictions of the device under test (DUT), yet they are simple enough that the non-linear optimization problem can be solved empirically in a reasonable amount of time. Feature extractors for BIT: A methodology for the built-in testing of RF devices integrated into SOPs is developed using additional hardware components. These hardware components correlate the high-bandwidth test response to low bandwidth signatures while extracting the test-critical features of the DUT. Supervised learning is used to map these extracted features, which otherwise are too complicated to decipher by plain mathematical analysis, into the specifications under test. Defect-based alternate testing of RF circuits: A methodology for the efficient testing of RF devices with low-cost defect-based alternate tests is developed. The signature of the DUT is probabilistically compared with a class of defect-free device signatures to explore possible corners under acceptable levels of process parameter variations. Such a defect filter applies discrimination rules generated by a supervised classifier and eliminates the need for a library of possible catastrophic defects.Ph.D.Committee Chair: Chatterjee, Abhijit; Committee Member: Durgin, Greg; Committee Member: Keezer, David; Committee Member: Milor, Linda; Committee Member: Sitaraman, Sures

Differential temperature sensors: Review of applications in the test and characterization of circuits, usage and design methodology

Differential temperature sensors can be placed in integrated circuits to extract a signature ofthe power dissipated by the adjacent circuit blocks built in the same silicon die. This review paper firstdiscusses the singularity that differential temperature sensors provide with respect to other sensortopologies, with circuit monitoring being their main application. The paper focuses on the monitoringof radio-frequency analog circuits. The strategies to extract the power signature of the monitoredcircuit are reviewed, and a list of application examples in the domain of test and characterizationis provided. As a practical example, we elaborate the design methodology to conceive, step bystep, a differential temperature sensor to monitor the aging degradation in a class-A linear poweramplifier working in the 2.4 GHz Industrial Scientific Medical—ISM—band. It is discussed how,for this particular application, a sensor with a temperature resolution of 0.02 K and a high dynamicrange is required. A circuit solution for this objective is proposed, as well as recommendations for thedimensions and location of the devices that form the temperature sensor. The paper concludes with adescription of a simple procedure to monitor time variability.Postprint (published version

BPF-based thermal sensor circuit for on-chip testing of RF circuits

A new sensor topology meant to extract figures of merit of radio-frequency analog integrated circuits (RF-ICs) was experimentally validated. Implemented in a standard 0.35 µm complementary metal-oxide-semiconductor (CMOS) technology, it comprised two blocks: a single metaloxide-semiconductor (MOS) transistor acting as temperature transducer, which was placed near the circuit to monitor, and an active band-pass filter amplifier. For validation purposes, the temperature sensor was integrated with a tuned radio-frequency power amplifier (420 MHz) and MOS transistors acting as controllable dissipating devices. First, using the MOS dissipating devices, the performance and limitations of the different blocks that constitute the temperature sensor were characterized. Second, by using the heterodyne technique (applying two nearby tones) to the power amplifier (PA) and connecting the sensor output voltage to a low-cost AC voltmeter, the PA’s output power and its central frequency were monitored. As a result, this topology resulted in a low-cost approach, with high linearity and sensitivity, for RF-IC testing and variability monitoring.This research was funded by Spanish AEI–Agencia Estatal de Investigación–grant number PID2019-103869RB-C33. (X.P.) has also received founds from the Spanish Ministry of Science, Innovation and Universities through Agencia Estatal de Investigación (AEI) (projects: HIPERCELLS, RTI2018-098392B-I00, and “Fiabilidad Inteligente”, PCI2020-112028).Peer ReviewedPostprint (published version

DC temperature measurements to characterize the central frequency and 3 dB bandwidth in mmW power amplifiers

This letter shows how a temperature sensor and a simple DC voltage multimeter can be used as instruments to determine the central frequency and 3 dB bandwidth of a 60 GHz linear power amplifier (PA). Compared to previous works, the DC temperature monitoring now proposed requires a much simpler and convenient measurement set-up. In this example, the temperature sensor is embedded in the same silicon die as the PA. Being placed in empty layout spaces next to it, it is proposed as a built-in test circuit.Peer ReviewedPostprint (author's final draft

Feasibility Evaluation of a Vibration-Based Leak Detection Technique for Sustainable Water Distribution Pipeline System Monitoring

Conventional water pipeline leak-detection surveys employ labor-intensive acoustic techniques, which are usually expensive and less useful for continuous monitoring of distribution pipelines. Based on a comprehensive review of literature and available commercial products, it has been recognized that despite previous studies and products attempting to address the limitations of the conventional surveys by proposing and evaluating a myriad of leak-detection techniques (LDTs), they lacked extensive validation on complex looped systems. Additionally, they offer limited compatibility with some pipe materials such as those made of plastic and may even fail to distinguish leaks from other system disturbances. A novel LDT that addresses some of these limitations is developed and evaluated in the current study using an experimental set-up that is representative of a real-world pipeline system and made of Polyvinyl Chloride (PVC) pipe. The studied LDT requires continuous monitoring of the change in the cross spectral density of surface vibration measured at discrete locations along the pipeline. This vibration-based LDT was hypothesized to be capable of not only detecting the onset of leakage, but also determining its relative severity in complex pipeline systems. Findings based on a two-phase, controlled experimental testing revealed that the proposed LDT is capable of detecting leakages and estimating their relative severities in a real-size, multi-looped pipeline system that is comprised of multiple joints, bends and pipes of multiple sizes. Furthermore, the sustainability merits of the proposed LDT for a representative application scenario are estimated. Specifically, life cycle costs and energy consumption for monitoring the large diameter pipelines in the water distribution system of the Charleston peninsula region in South Carolina are estimated by developing conceptual prototypes of the sensing, communication and computation schemes for practically employing the proposed LDT. The prototype designs are informed by the knowledge derived from the two-phase experimental testing campaign. Overall, the proposed study contributes to the body of knowledge on water pipeline leak detection, specifically to non-intrusive vibration-based monitoring, applications on plastic pipelines, and smart and sustainable network-wide continuous monitoring schemes

NASA SBIR abstracts of 1991 phase 1 projects

The objectives of 301 projects placed under contract by the Small Business Innovation Research (SBIR) program of the National Aeronautics and Space Administration (NASA) are described. These projects were selected competitively from among proposals submitted to NASA in response to the 1991 SBIR Program Solicitation. The basic document consists of edited, non-proprietary abstracts of the winning proposals submitted by small businesses. The abstracts are presented under the 15 technical topics within which Phase 1 proposals were solicited. Each project was assigned a sequential identifying number from 001 to 301, in order of its appearance in the body of the report. Appendixes to provide additional information about the SBIR program and permit cross-reference of the 1991 Phase 1 projects by company name, location by state, principal investigator, NASA Field Center responsible for management of each project, and NASA contract number are included

Surface and inter-phase analysis of Composite Materials using Electromagnetic Techniques based on SQUID Sensors

In this thesis an electromagnetic characterization and a non-destructive evaluation of new advanced composite materials, Carbon Fiber Reinforced Polymers (CFRP) and Fiber-Glass Aluminium (FGA) laminates, using an eddy-current technique based on HTS dc-SQUID (Superconductive QUantum Interference Device) magnetometer is proposed. The main goal of this thesis is to propose a prototype based on a superconducting sensor, such as SQUID, to guarantee a more accuracy in the quality control at research level of the composite materials employed in the aeronautical applications. A briefly introduction about the superconductivity, a complete description of the SQUID properties and its basic working principles have been reported. Moreover, an overview of the most widely used non destructive technique employed in several industrial and research fields have been described. Particular attention is given to the eddy current testing and the technical improvement obtained using SQUID in NDE. The attention has been focused on two particular application, that are the main topics of this thesis. The first concerns with the investigation of the damage due to impact loading on the composites materials, and the second is the study of the corrosion process on the metallic surface. The electrical and mechanical properties of the tested advanced composite materials, such as Carbon Fiber Reinforced Polymers (CFRPs) and Fiber-glass Aluminium (FGA) laminates are investigated. The experimental results concern the non-destructive evaluation of impact loading on the CFRPs and FGA composites, by means of the electromagnetic techniques; the investigation of the electromechanical effect in the CFRPs using the SQUID based prototype and the AFM analyses; and the study of corrosion activity of the metallic surface using magnetic field measurement

A review of automated solar photovoltaic defect detection systems : approaches, challenges, and future orientations

The development of Photovoltaic (PV) technology has paved the path to the exponential growth of solar cell deployment worldwide. Nevertheless, the energy efficiency of solar cells is often limited by resulting defects that can reduce their performance and lifespan. Therefore, it is crucial to identify a set of defect detection approaches for predictive maintenance and condition monitoring of PV modules. This paper presents a comprehensive review of different data analysis methods for defect detection of PV systems with a high categorisation granularity in terms of types and approaches for each technique. Such approaches, introduced in the literature, were categorised into Imaging-Based Techniques (IBTs) and Electrical Testing Techniques (ETTs). Although several review papers have investigated recent solar cell defect detection techniques, they do not provide a comprehensive investigation including IBTs and ETTs with a greater granularity of the different types of each for PV defect detection systems. Types of IBTs were categorised into Infrared Thermography (IRT), Electroluminescence (EL) imaging, and Light Beam Induced Current (LBIC). On the other hand, ETTs were categorised into Current-Voltage (I-V) characteristics analysis, Earth Capacitance Measurements (ECM), Time Domain Reflectometry (TDR), Power Losses Analysis (PLA), and Voltage and Current Measurements (VCM). Approaches based on digital/signal processing and Machine Learning (ML) models for each method are included where relevant. Moreover, the paper critically analyses the advantages and disadvantages of each of the adopted techniques, which can be referred to by future studies to identify the most suitable method considering the use-case’s requirements and setting. The adoption of each of the reviewed techniques depends on several factors, including the deployment scale, the targeted defects for detection, and the required location of defect analysis in the PV system, which are expanded further in the presented analysis. From a high-level perspective, while IBTs provide a high-resolution visual representation of the module surface, allowing for the detection and diagnosis of small structural defects that may be missed by other techniques, ETTs can detect electrical faults beyond the PV module’s surface. On the IBT level, the most notable adopted techniques in the literature are IRT- and EL-based. While IRT techniques are more practical for large-scale applications than EL imaging, the latter is considered a non-intrusive technique that is highly efficient in localising defects of solar cells. The paper also discusses challenges observed in the state-of-the-art related to data availability, real-time monitoring, accurate measurements, computational efficiency, and dataset distribution, and reviews data pre-processing and augmentation approaches that can address some of these challenges. Furthermore, potential future orientations are identified, addressing the limitations of PV defect detection systems