Sequential circuit design in quantum-dot cellular automata

In this work we present a novel probabilistic modeling scheme for sequential circuit design in quantum-dot cellular automata(QCA) technology. Clocked QCA circuits possess an inherent direction for flow of information which can be effectively modeled using Bayesian networks (BN). In sequential circuit design this presents a problem due to the presence of feedback cycles since BN are direct acyclic graphs (DAG). The model presented in this work can be constructed from a logic design layout in QCA and is shown to be a dynamic Bayesian Network (DBN). DBN are very powerful in modeling higher order spatial and temporal correlations that are present in most of the sequential circuits. The attractive feature of this graphical probabilistic model is that that it not only makes the dependency relationships amongst node explicit, but it also serves as a computational mechanism for probabilistic inference. We analyze our work by modeling clocked QCA circuits for SR F/F, JK F/F and RAM designs

Quantum-dot Cellular Automata: Review Paper

Quantum-dot Cellular Automata (QCA) is one of the most important discoveries that will be the successful alternative for CMOS technology in the near future. An important feature of this technique, which has attracted the attention of many researchers, is that it is characterized by its low energy consumption, high speed and small size compared with CMOS.  Inverter and majority gate are the basic building blocks for QCA circuits where it can design the most logical circuit using these gates with help of QCA wire. Due to the lack of availability of review papers, this paper will be a destination for many people who are interested in the QCA field and to know how it works and why it had taken lots of attention recentl

Fault and Defect Tolerant Computer Architectures: Reliable Computing With Unreliable Devices

This research addresses design of a reliable computer from unreliable device technologies. A system architecture is developed for a fault and defect tolerant (FDT) computer. Trade-offs between different techniques are studied and yield and hardware cost models are developed. Fault and defect tolerant designs are created for the processor and the cache memory. Simulation results for the content-addressable memory (CAM)-based cache show 90% yield with device failure probabilities of 3 x 10(-6), three orders of magnitude better than non fault tolerant caches of the same size. The entire processor achieves 70% yield with device failure probabilities exceeding 10(-6). The required hardware redundancy is approximately 15 times that of a non-fault tolerant design. While larger than current FT designs, this architecture allows the use of devices much more likely to fail than silicon CMOS. As part of model development, an improved model is derived for NAND Multiplexing. The model is the first accurate model for small and medium amounts of redundancy. Previous models are extended to account for dependence between the inputs and produce more accurate results

Design of Sequential Circuit Using Quantum-Dot Cellular Automata (QCA)

Quantum dot cellular autometa presents a promissing nanoscale technology for replacement of conventional cmos based circuits.In this paper we introduce qca logic gates such has qca inverter and qca majority gate.This paper design the sequential logic gates.such as D latch,SR latch,JK latch,T flipflop,D flipflop,2 bit counter,4 bit shift register.These designs are captured and simulated using a design calld QCA designer

ANALYSIS AND MODULATION OF MOLECULAR QUANTUM-DOT CELLULAR AUTOMATA (QCA) DEVICES

Field-Coupled nanocomputing (FCN) paradigms offer fundamentally new approaches for digital computing without involving current transistors. Such paradigms perform computations using local field interactions between nanoscale building blocks which are organized with purposes. Among several FCN paradigms currently under active investigation, the Molecular Quantum-dot Cellular Automata (MQCA) is found to be the most promising and its unique features make it attractive as a candidate for post-CMOS nanocomputing. MQCA is based on electrostatic interactions among quantum cells with nanometer scale eliminating the need of charge transportation, hence its energy consumption is significantly decreased. Meanwhile it also possesses the potential of high throughput if efficient pipelining of information propagation is introduced. This could be realized adopting external clock signals which precisely control the adiabatic switching and direction of data flow in MQCA circuits. In this work, in order to model MQCA as electronic devices and analyze its information propagation with clock taken into account, an effective algorithm based on ab-initio simulations and modelling of molecular interactions has been applied in presence of a proposed clock mechanism for MQCA, including the binary wire, the wire bus and the majority voter. The quantitative results generated depict compelling clocked information propagation phenomena of MQCA devices and most importantly, provide crucial feedback for future MQCA experimental implementation

Fault tolerance issues in nanoelectronics

The astonishing success story of microelectronics cannot go on indefinitely. In fact, once devices reach the few-atom scale (nanoelectronics), transient quantum effects are expected to impair their behaviour. Fault tolerant techniques will then be required. The aim of this thesis is to investigate the problem of transient errors in nanoelectronic devices. Transient error rates for a selection of nanoelectronic gates, based upon quantum cellular automata and single electron devices, in which the electrostatic interaction between electrons is used to create Boolean circuits, are estimated. On the bases of such results, various fault tolerant solutions are proposed, for both logic and memory nanochips. As for logic chips, traditional techniques are found to be unsuitable. A new technique, in which the voting approach of triple modular redundancy (TMR) is extended by cascading TMR units composed of nanogate clusters, is proposed and generalised to other voting approaches. For memory chips, an error correcting code approach is found to be suitable. Various codes are considered and a lookup table approach is proposed for encoding and decoding. We are then able to give estimations for the redundancy level to be provided on nanochips, so as to make their mean time between failures acceptable. It is found that, for logic chips, space redundancies up to a few tens are required, if mean times between failures have to be of the order of a few years. Space redundancy can also be traded for time redundancy. As for memory chips, mean times between failures of the order of a few years are found to imply both space and time redundancies of the order of ten