Nanocluster-rich SiO2 layers produced by ion beam synthesis: electrical and optoelectronic properties

The aim of this work was to find a correlation between the electrical, optical and microstructural properties of thin SiO2 layers containing group IV nanostructures produced by ion beam synthesis. The investigations were focused on two main topics: The electrical properties of Ge- and Si-rich oxide layers were studied in order to check their suitability for non-volatile memory applications. Secondly, photo- and electroluminescence (PL and EL) results of Ge-, Si/C- and Sn-rich SiO2 layers were compared to electrical properties to get a better understanding of the luminescence mechanism

Optimization and evaluation of variability in the programming window of a flash cell with molecular metal-oxide storage

We report a modeling study of a conceptual nonvolatile memory cell based on inorganic molecular metal-oxide clusters as a storage media embedded in the gate dielectric of a MOSFET. For the purpose of this paper, we developed a multiscale simulation framework that enables the evaluation of variability in the programming window of a flash cell with sub-20-nm gate length. Furthermore, we studied the threshold voltage variability due to random dopant fluctuations and fluctuations in the distribution of the molecular clusters in the cell. The simulation framework and the general conclusions of our work are transferrable to flash cells based on alternative molecules used for a storage media

Secure HfO2 based charge trap EEPROM with lifetime and data retention time modeling

Trusted computing is currently the most promising security strategy for cyber physical systems. Trusted computing platform relies on securely stored encryption keys in the on-board memory. However, research and actual cases have shown the vulnerability of the on-board memory to physical cryptographic attacks. This work proposed an embedded secure EEPROM architecture employing charge trap transistor to improve the security of storage means in the trusted computing platform. The charge trap transistor is CMOS compatible with high dielectric constant material as gate oxide which can trap carriers. The process compatibility allows the secure information containing memory to be embedded with the CPU. This eliminates the eavesdropping and optical observation. This effort presents the secure EEPROM cell, its high voltage programming control structure and an interface architecture for command and data communication between the EEPROM and CPU. The interface architecture is an ASIC based design that exclusively for the secure EEPROM. The on-board programming capability enables adjustment of programming voltages and accommodates EEPROM threshold variation due to PVT to optimize lifetime. In addition to the functional circuitry, this work presents the first model of lifetime and data retention time tradeoff for this new type of EEPROM. This model builds the bridge between desired data retention time and lifetime while producing the corresponding programming time and voltage

Design and development of an embedded flash memory integrated simulator for the automotive microcontroller firmware validation

Applicazioni automotive possono compromettere la sicurezza delle persone pertanto i componenti devono essere affidabili in qualsiasi condizione operativa. L'affidabilità può essere raggiunta testando i dispositivi dopo la produzione, progettare il test è un compito delicato in quanto non sono presenti fisicamente i primi prototipi del dispositivo. Realizziamo un simulatore di memorie flash integrate di un microcontrollore automotive per facilitare la progettazione dei tes

Etude d'architectures et d'empilements innovants de mémoires Split-Gate (grille séparée) à couche de piégeage discret

Du fait de l'augmentation de la demande de produits pour les applications grand public, industrielles et automobiles, des mémoires embarquées fiables et à faible coût de fabrication sont de plus en plus demandées. Dans ce contexte, les mémoires split-gate à piégeage discret sont proposées pour des microcontrôleurs. Elles combinent l'avantage d'une couche de stockage discrète et de la con guration split-gate. Durant ce travail de recherche, des mémoires split-gate à couche de piégeage discret ayant des longueurs de grille de 20nm sont présentées pour la première fois. Celles-ci on été réalisées avec des nanocristaux de silicium (Si-nc), du nitrure de silicium (SiN) ou un hybride Si-nc/SiN avec diélectrique de control de type SiO2 ou AlO et sont comparées en termes de performances lors des procédures d'eff acement et de rétention. Ensuite, la miniaturisation des mémoires split-gate à piégeage de charge est étudié, en particulier au travers de l'impact de la réduction de la longueur de grille sur la fenêtre de mémorisation, la rétention et la consommation. Le rôle des défauts dans le diélectrique de contrôle (alumine) utilisé dans les mémoires de type TANOS a été étudié. Des travaux ont été menés pour déterminer l'origine des pièges dans ce matériau, par le biais de la simulation atomistique ainsi que d'analyses physico-chimiques précises. Nous avons montré que la concentration de pièges dans AlO pouvait être réduite par ajustement des conditions de procédé de fabrication, débouchant ainsi sur l'amélioration de la rétention dans les mémoires à piégeage de charge. Ce résultat est convenable pour les applications de type embarquéDue to the increasing demand for consumer, industrial and automotive products, highly reliable, and low integration cost embedded memories are more and more required. In this context, split-gate charge trap memories were proposed for microcontroller products, combining the advantage of a discrete storage layer and of the split-gate con guration. In this thesis, split-gate charge trap memories with electrical gate length down to 20nm are presented for the 1st time. Silicon nanocristals (Si-nc), or silicon nitride (SiN) and hybrid Si-nc/SiN based split-gate memories, with SiO2 or AlO control dielectrics, are compared in terms of program erase and retention. Then, the scalability of split-gate charge trap memories is studied, investigating the impact of gate length reduction on the memory window, retention and consumption. We thus studied the role of defects on alumina control dielectric employed in TANOS-like memory. We used atomistic simulation, consolidated by a detailed alumina physico-chemical material analysis, to investigate the origin of traps in alumina. We showed that the trap concentration in AlO can be decreased by adjusting the process conditions leading to improved retention behaviour in charge trap memory, suitable for embedded applications.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

A model for programming characteristics of Sonos type flash with high-kappa dielectrics

Silicon Oxide Nitride Oxide Silicon (SONOS) FLASH memories have recently gained a lot of attention due to better retention and scaling opportunities over the conventional Floating Gate FLASH memories. The constant demand for device scaling, to attain higher density, higher performance, and low cost per bit, has posed charge leakage problems. SONOS type devices with high-kappa storage layers and/or high-kappa blocking oxide have been proposed to alleviate the demand for constant tunnel oxide scaling. In comparison to conventional FLASH, these devices operate at lower voltages, exhibit higher programming speeds, comparable retention times, less over-erase problem and better compatibility with low power CMOS logic; The objective of this thesis is to develop a comprehensive model which can be used to obtain the programming characteristics, i.e., shift in threshold voltage vs. program time, for trap-based FLASH memories with high-kappa dielectrics. The proposed model is used to obtain the programming characteristics for SONOS type devices. The results from this model are compared with the experimental results and in general the agreement is good. For SONOS type devices with high-kappa blocking oxides, the density of available nitride traps for charge storage is shown to have a linear dependence with the potential energy difference between the silicon substrate and the nitride storage for different gate biases. The model is also used to get an estimate of available trap energy levels in the nitride layer as a function of applied voltage

High dielectric constant materials in SONOS-type non- volatile memory structures

Ph.DDOCTOR OF PHILOSOPH