Statistical Power Supply Dynamic Noise Prediction in Hierarchical Power Grid and Package Networks

One of the most crucial high performance systems-on-chip design challenge is to front their power supply noise sufferance due to high frequencies, huge number of functional blocks and technology scaling down. Marking a difference from traditional post physical-design static voltage drop analysis, /a priori dynamic voltage drop/evaluation is the focus of this work. It takes into account transient currents and on-chip and package /RLC/ parasitics while exploring the power grid design solution space: Design countermeasures can be thus early defined and long post physical-design verification cycles can be shortened. As shown by an extensive set of results, a carefully extracted and modular grid library assures realistic evaluation of parasitics impact on noise and facilitates the power network construction; furthermore statistical analysis guarantees a correct current envelope evaluation and Spice simulations endorse reliable result

Effective network grid synthesis and optimization for high performance very large scale integration system design

制度:新 ; 文部省報告番号:甲2642号 ; 学位の種類:博士(工学) ; 授与年月日:2008/3/15 ; 早大学位記番号:新480

Hybrid Amorphous-Selenium/CMOS Low-Light Imager

This thesis aims to demonstrate a low-light imager capable of moonlight-level imag- ing by combining a custom-designed complementary-metal-oxide-semiconductor (CMOS) pixel array with amorphous selenium (a-Se) as its photosensor. Because of the low dark current of a-Se compared to standard silicon photodiodes, this hybrid structure could enable imagers fabricated in standard mixed-signal CMOS processes to achieve low- light imaging. Such hybrid imagers could have low-light performances comparable to other low-light imagers fabricated in specialized CMOS image-sensor processes. The 320 (H) x 240 (V) imager contains four different pixel designs arranged in four quadrants, with pixel pitches of 7.76 μm x 7.76 μm in quadrants 1 to 3 and 7.76 μm x 8.66 μm in quadrant 4 (Q4). The different quadrants are built to examine various performance-enhancing circuit designs and techniques, including series-stacked devices for leakage suppression, charge-injection suppression that uses dummy transistors, and a programmable dual-capacity design for extended pixel dynamic range. The imager- performance parameters, such as noise, dynamic range, conversion gain, linearity, and full-well capacity were simulated and experimentally verified. This work will also de- scribe the external hardware and software designs used to operate the imager. This thesis summarizes and reports the overall electrical and optical performance of pixels in quadrant 1. The observed signal-to-noise ratio (SNR) of above 20 dB at an illuminance of 0.267 lux demonstrates that the imager can produce excellent images under moonlight-imaging conditions. This was achieved mainly through utilization of the long integration time enabled by circuit techniques implemented at the pixel level, as well as the low dark current of a-Se

High-Speed and Low-Energy On-Chip Communication Circuits.

Continuous technology scaling sharply reduces transistor delays, while fixed-length global wire delays have increased due to less wiring pitch with higher resistance and coupling capacitance. Due to this ever growing gap, long on-chip interconnects pose well-known latency, bandwidth, and energy challenges to high-performance VLSI systems. Repeaters effectively mitigate wire RC effects but do little to improve their energy costs. Moreover, the increased complexity and high level of integration requires higher wire densities, worsening crosstalk noise and power consumption of conventionally repeated interconnects. Such increasing concerns in global on-chip wires motivate circuits to improve wire performance and energy while reducing the number of repeaters. This work presents circuit techniques and investigation for high-performance and energy-efficient on-chip communication in the aspects of encoding, data compression, self-timed current injection, signal pre-emphasis, low-swing signaling, and technology mapping. The improved bus designs also consider the constraints of robust operation and performance/energy gains across process corners and design space. Measurement results from 5mm links on 65nm and 90nm prototype chips validate 2.5-3X improvement in energy-delay product.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/75800/1/jseo_1.pd

Power Converters in Power Electronics

In recent years, power converters have played an important role in power electronics technology for different applications, such as renewable energy systems, electric vehicles, pulsed power generation, and biomedical sciences. Power converters, in the realm of power electronics, are becoming essential for generating electrical power energy in various ways. This Special Issue focuses on the development of novel power converter topologies in power electronics. The topics of interest include, but are not limited to: Z-source converters; multilevel power converter topologies; switched-capacitor-based power converters; power converters for battery management systems; power converters in wireless power transfer techniques; the reliability of power conversion systems; and modulation techniques for advanced power converters