On-Chip Digital Decoupling Capacitance Methodology

Signal integrity has become a major problem in digital IC design. One cause of this problem is device scaling which results in a sharp reduction of supply voltage, creating stringent noise margin requirements to ensure functionality. Reductions in feature size also result in increased clock speeds leading to many different high frequency noise producing components. As on-chip area increases to allow for more computational capability, so does the amount of digital logic to be placed, magnifying the effects of noisy interconnect structures. Supply noise, modeled as AV = Ldi/dt , is caused by rapid current spikes during a rise or fall time. Decoupling capacitors often fill empty on-chip space for the purpose of limiting this noise. This work introduces a novel methodology that attempts to quantify and locate decoupling capacitors within a power distribution network. The bondwire attached on the periphery of the face of the die is taken to be the dominant source of inductance. It is shown that distributing capacitance closer to the switching elements is most effective at reducing supply noise. A chip has been designed using TSMC 90 nm technology that implements the ideas presented in this work. Simulation results show that noise fluctuations are high enough such that random placement of decoupling capacitance is not effective for large digital structures. The amount of interconnect generated on-chip noise increases with area, resulting in the need for an optimal decoupling scheme. As scaling continues, supply voltages and noise margins will decrease, creating the need for a robust decoupling capacitance methodology

Printed circuit board power distribution network modeling, analysis and design, and, statistical crosstalk analysis for high speed digital links

High-speed digital systems are moving to higher data rates and smaller supply voltages as the scale of integration goes smaller. With the smaller bit periods and the smaller operating voltages, the tolerable timing and noise margins are reducing. There are many sources of disturbances contributing to the tolerance margins. These margins have to account for inter symbol interference (ISI), reflections, jitter, noise from power distribution networks (PDN) and crosstalk. An important task during the design phase of the system is to find and mitigate the noise from such sources. This thesis proposes modeling and analysis methodology to resolve some of the problems while proposing relevant design methodologies to reduce the system design cycles. PDN design forms a critical part of a high-speed digital design to provide a low-noise power supply to the integrated circuits (ICs) within some peak voltage ripple for normal functioning. Switching of transistors in the IC leads to a high-frequency current draw and generates the simultaneous switching noise (SSN), which propagates along the PDN from the chip to the PCB and causes several EMI and SI problems. A physics-based modeling approach for PCB PDN is proposed which is used for analysis and design guideline development. A design methodology is developed which guides the designer to make better design decisions, knowing the impact on PDN performance without the use of full-wave tools. Crosstalk forms a critical part of the budget, and if ignored, can lead to design failures. A statistical method to find the distribution of crosstalk at the victim using the single bit response principle is proposed. The methodology is extended to multiple-aggressor system, and, can be used to identify worst case crosstalk and find dominant crosstalk contributors in a system. --Abstract, page iii

CONTROL STRATEGIES OF DC MICROGRID TO ENABLE A MORE WIDE-SCALE ADOPTION

Microgrids are gaining popularity in part for their ability to support increased penetration of distributed renewable energy sources, aiming to meet energy demand and overcome global warming concerns. DC microgrid, though appears promising, introduces many challenges in the design of control systems in order to ensure a reliable, secure and economical operation. To enable a wider adoption of DC microgrid, this dissertation examines to combine the characteristics and advantages of model predictive control (MPC) and distributed droop control into a hierarchy and fully autonomous control of the DC microgrid. In addition, new maximum power point tracking technique (MPPT) for solar power and active power decoupling technique for the inverter are presented to improve the efficiency and reliability of the DC microgrid. With the purpose of eliminating the oscillation around the maximum power point (MPP), an improved MPPT technique was proposed by adding a steady state MPP determination algorithm after the adaptive perturb and observe method. This control method is proved independent with the environmental conditions and has much smaller oscillations around the MPP compared to existing ones. Therefore, it helps increase the energy harvest efficiency of the DC microgrid with less continuous DC power ripple. A novel hierarchy strategy consisting of two control loops is proposed to the DC microgrid in study, which is composed of two PV boost converters, two battery bi-directional converters and one multi-level packed-u-cell inverter with grid connected. The primary loop task is the control of each energy unit in the DC microgrid based on model predictive current control. Compared with traditional PI controllers, MPC speeds up the control loop since it predicts error before the switching signal is applied to the converter. It is also free of tuning through the minimization of a flexible user-defined cost function. Thus, the proposed primary loop enables the system to be expandable by adding additional energy generation units without affecting the existing ones. Moreover, the maximum power point tracking and battery energy management of each energy unit are included in this loop. The proposed MPC also achieves unity power factor, low grid current total harmonics distortion. The secondary loop based on the proposed autonomous droop control identifies the operation modes for each converter: current source converter (CSC) or voltage source converter (VSC). To reduce the dependence on the high bandwidth communication line, the DC bus voltage is utilized as the trigger signal to the change of operation modes. With the sacrifice of small variations of bus voltage, a fully autonomous control can be realized. The proposed distributed droop control of different unit converters also eliminates the potential conflicts when more than two converters compete for the VSC mode. Single-phase inverter systems in the DC microgrid have low frequency power ripple, which adversely affects the system reliability and performance. A power decoupling circuit based on the proposed dual buck converters are proposed to address the challenges. The topology is free of shoot-through and deadtime concern and the control is independent with that of the main power stage circuit, which makes the design simpler and more reliable. Moreover, the design of both PI and MPC controllers are discussed and compared. While, both methods present satisfied decoupling performances on the system, the proposed MPC is simpler to be implemented. In conclusion, the DC microgrid may be more widely adopted in the future with the proposed control strategies to address the current challenges that hinder its further development