A plug-and-play ripple mitigation approach for DC-links in hybrid systems

© 2016 IEEE.In this paper, a plug-and-play ripple mitigation technique is proposed. It requires only the sensing of the DC-link voltage and can operate fully independently to remove the low-frequency voltage ripple. The proposed technique is nonintrusive to the existing hardware and enables hot-swap operation without disrupting the normal functionality of the existing power system. It is user-friendly, modular and suitable for plug-and-play operation. The experimental results demonstrate the effectiveness of the ripple-mitigation capability of the proposed device. The DC-link voltage ripple in a 110 W miniature hybrid system comprising an AC/DC converter and two resistive loads is shown to be significantly reduced from 61 V to only 3.3 V. Moreover, it is shown that with the proposed device, the system reliability has been improved by alleviating the components' thermal stresses

Direct control strategy for a four-level three-phase flying-capacitor inverter

A direct predictive control strategy is proposed for a three-phase four-level flying-capacitor (FC) inverter in this paper. The balancing of the FC voltages, a challenge in applications with small capacitors and low switching frequencies, is done without any modulation, simply using tables calculated offline. These allow the realization of fast-dynamics output currents with reduced dv/dt in the output voltages and reduced switching frequencies. Moreover, no interharmonics are created when operating at low switching frequencies and with reference currents containing multiple harmonic components, which is a key feature for active power filters. Simulations and experimental results are presented to demonstrate the excellent performance of the direct control strategy in comparison with a conventional pulsewidth-modulation control technique, mostly for operation at low switching frequencies

Power Quality Enhancement in Electricity Grids with Wind Energy Using Multicell Converters and Energy Storage

In recent years, the wind power industry is experiencing a rapid growth and more wind farms with larger size wind turbines are being connected to the power system. While this contributes to the overall security of electricity supply, large-scale deployment of wind energy into the grid also presents many technical challenges. Most of these challenges are one way or another, related to the variability and intermittent nature of wind and affect the power quality of the distribution grid. Power quality relates to factors that cause variations in the voltage level and frequency as well as distortion in the voltage and current waveforms due to wind variability which produces both harmonics and inter-harmonics. The main motivation behind work is to propose a new topology of the static AC/DC/AC multicell converter to improve the power quality in grid-connected wind energy conversion systems. Serial switching cells have the ability to achieve a high power with lower-size components and improve the voltage waveforms at the input and output of the converter by increasing the number of cells. Furthermore, a battery energy storage system is included and a power management strategy is designed to ensure the continuity of power supply and consequently the autonomy of the proposed system. The simulation results are presented for a 149.2 kW wind turbine induction generator system and the results obtained demonstrate the reduced harmonics, improved transient response, and reference tracking of the voltage output of the wind energy conversion system.Peer reviewedFinal Accepted Versio

Modelling and regulation of dual-output LCLC resonant converters

The analysis, design and control of 4th-order LCLC voltage-output series-parallel resonant converters (SPRCs) for the provision of multiple regulated outputs, is described. Specifically, state-variable concepts are employed and new analysis techniques are developed to establish operating mode boundaries with which to describe the internal behaviour of a dual-output resonant converter topology. The designer is guided through the most important criteria for realising a satisfactory converter, and the impact of parameter choices on performance is explored. Predictions from the resulting models are compared with those obtained from SPICE simulations and measurements from a prototype power supply under closed loop control

A hybrid cavity and parallel-plate PEEC method for analysis of complex power net area fills, and a tool development for peak distortion analysis

Modern ASICs and FPGAs are becoming more and more dense, which is causing an increasing demand of the current draw from the power distribution network (PDN). And one of the main design objectives of a power distribution network is to reduce the voltage noise ripple below a specified allowable limit. Although the target impedance is a commonly used criterion in most PDN designs, it may not be efficient because it\u27s usually rather pessimistic. Herein a time domain voltage ripple decomposition approach is proposed to avoid overdesign as well as provide design guidance to PI engineers. Based on a physics-based circuit model for PDN and a switching current generator including both high frequency switching and low frequency power gating, the total voltage ripple can be divided into several components. Each component will have a one-to-one correspondence to the real PDN geometry. Thus design curves can also be derived, which can guide PI engineers when making design decisions. Peak distortion analysis (PDA) is commonly used to find the worst-case eye diagram and data pattern. Compared to traditional long transient simulations, PDA can significantly reduce the computation time by only taking into consideration the worst case. Generally PDA is based on a superposition technique with a single bit response (SBR), which requires the system to be linear time invariant (LTI) or can be well approximated as an LTI system. SBR is no longer applicable for systems which have different rising and falling edge responses due to asymmetric I/O design or mismatches between pull-up and pull-down drivers. Also sometimes the nonlinearity can extend beyond the edge transitions which can result from the voltage noise on the power distribution network (PDN). Herein PDA based on the superposition of multiple edge responses (MER) is proposed to account for a non-LTI system as well as asymmetric rising and falling edges --Abstract, page iii

High-speed simulation of PCB emission and immunity with frequency-domain IC/LSI source models

Some recent results from research conducted in the EMC group at Okayama University are reviewed. A scheme for power-bus modeling with an analytical method is introduced. A linear macro-model for ICs/LSIs, called the LECCS model, has been developed for EMI and EMS simulation. This model has a very simple structure and is sufficiently accurate. Combining the LECCS model with analytical simulation techniques for power-bus resonance simulation provides a method for high-speed EMI simulation and decoupling evaluation related to PCB and LSI design. A useful explanation of the common-mode excitation mechanism, which utilizes the imbalance factor of a transmission line, is also presented. Some of the results were investigated by implementing prototypes of a high-speed EMI simulator, HISES. </p

Printed circuit board power distribution network modeling, analysis and design, and, statistical crosstalk analysis for high speed digital links

High-speed digital systems are moving to higher data rates and smaller supply voltages as the scale of integration goes smaller. With the smaller bit periods and the smaller operating voltages, the tolerable timing and noise margins are reducing. There are many sources of disturbances contributing to the tolerance margins. These margins have to account for inter symbol interference (ISI), reflections, jitter, noise from power distribution networks (PDN) and crosstalk. An important task during the design phase of the system is to find and mitigate the noise from such sources. This thesis proposes modeling and analysis methodology to resolve some of the problems while proposing relevant design methodologies to reduce the system design cycles. PDN design forms a critical part of a high-speed digital design to provide a low-noise power supply to the integrated circuits (ICs) within some peak voltage ripple for normal functioning. Switching of transistors in the IC leads to a high-frequency current draw and generates the simultaneous switching noise (SSN), which propagates along the PDN from the chip to the PCB and causes several EMI and SI problems. A physics-based modeling approach for PCB PDN is proposed which is used for analysis and design guideline development. A design methodology is developed which guides the designer to make better design decisions, knowing the impact on PDN performance without the use of full-wave tools. Crosstalk forms a critical part of the budget, and if ignored, can lead to design failures. A statistical method to find the distribution of crosstalk at the victim using the single bit response principle is proposed. The methodology is extended to multiple-aggressor system, and, can be used to identify worst case crosstalk and find dominant crosstalk contributors in a system. --Abstract, page iii

INVESTIGATION OF TECHNIQUES FOR REDUCING UNINTENTIONAL ELECTROMAGNETIC EMISSIONS FROM ELECTRONIC CIRCUITS AND SYSTEMS

This dissertation describes three independent studies related to techniques for reducing unintentional electromagnetic emissions from electronic circuits and systems. The topics covered are: low-inductance multi-layer ceramic capacitor for high frequency circuit board decoupling, the application of imbalance difference model to various circuit board and cable geometries, and balanced cable interface for reducing common-mode currents from power inverter. The first chapter discusses the importance and the meaning of the connection inductance associated with MLCCs and analyzes the effect of plate orientation in MLCCs. It demonstrates that vertically oriented plates have no more or less inductance than horizontally oriented plates when the overall dimensions of the plate stack are similar. Decoupling capacitance options at the various levels of a high-speed circuit is investigated to determine the range of frequencies that decoupling at each level is likely to be is effective. Innovative low-inductance capacitive-stem capacitor configurations are described and their connection impedance is compared to that of standard surface-mounted capacitors. The second chapter investigates the imbalance difference model that is a method for modeling how differential-mode signal currents are converted to common-mode noise currents. Various cable geometries to determine how well imbalance factor`s values of DM-to-CM conversion compare to full-wave calculations are explored. The imbalance difference model can be applied to cables with more than two conductors are demonstrated. The third chapter investigates the balanced cable interface for reducing common-mode currents from power inverter. The concept of a balancing network to reduce the common-mode currents on power inverter cables above 30 MHz is introduced. An experimental test set-up is used to demonstrate the effect of a balancing network on the common-mode current, differential-mode current and the common-mode rejection ratio on a balanced cable with an imbalanced termination. The balancing network is also evaluated using a 3-phase brushless DC motor driver to verify its effectiveness in a real application